From: Jim Liu <jim.t90615@gmail.com>
Date: Tue, 13 Sep 2022 06:23:15 +0000 (+0800)
Subject: pinctrl: nuvoton: fix set persist error
X-Git-Tag: v2025.01-rc5-pxa1908~1253^2~7
X-Git-Url: http://git.dujemihanovic.xyz/img/login.html?a=commitdiff_plain;h=45455e8ff5634e77aede803f9a772dba08b9674f;p=u-boot.git

pinctrl: nuvoton: fix set persist error

CA9C is cortex A9 watchdog reset control bit.
if device set persist mode, it shouldn't set this bit.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
---

diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
index f6e20415e2..31678f5537 100644
--- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
@@ -1388,10 +1388,10 @@ static int npcm7xx_gpio_reset_persist(struct udevice *dev, unsigned int banknum,
 	dev_dbg(dev, "set gpio persist, bank %d, enable %d\n", banknum, enable);
 
 	if (enable) {
-		regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD0RCR, BIT(num) | CA9C_RESET, 0);
-		regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD1RCR, BIT(num) | CA9C_RESET, 0);
-		regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD2RCR, BIT(num) | CA9C_RESET, 0);
-		regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_CORSTC, BIT(num) | CA9C_RESET, 0);
+		regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD0RCR, BIT(num), 0);
+		regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD1RCR, BIT(num), 0);
+		regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD2RCR, BIT(num), 0);
+		regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_CORSTC, BIT(num), 0);
 	} else {
 		regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD0RCR, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET);
 		regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD1RCR, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET);