From f4f57c58b5899efbad2f0d9c9dd8d44b0619395e Mon Sep 17 00:00:00 2001
From: =?utf8?q?Heiko=20St=C3=BCbner?= <heiko@sntech.de>
Date: Mon, 20 Mar 2017 12:40:33 +0100
Subject: [PATCH] rockchip: rk3188: Setup the armclk in spl
The armclk starts in slow mode (24MHz) on the rk3188, which results in U-Boot
startup taking a lot of time (U-Boot itself, but also the rc4 decoding done
in the bootrom).
With default pmic settings we can always reach a safe frequency of 600MHz
which is also the frequency the proprietary loader left the armclk at,
without needing access to the systems pmic.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
---
arch/arm/mach-rockchip/rk3188-board-spl.c | 24 +++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c
index 117f6b8f42..c3e174db9e 100644
--- a/arch/arm/mach-rockchip/rk3188-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3188-board-spl.c
@@ -4,6 +4,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <clk.h>
#include <common.h>
#include <debug_uart.h>
#include <dm.h>
@@ -76,6 +77,27 @@ u32 spl_boot_mode(const u32 boot_device)
return MMCSD_MODE_RAW;
}
+static int setup_arm_clock(void)
+{
+ struct udevice *dev;
+ struct clk clk;
+ int ret;
+
+ ret = rockchip_get_clk(&dev);
+ if (ret)
+ return ret;
+
+ clk.id = CLK_ARM;
+ ret = clk_request(dev, &clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_set_rate(&clk, 600000000);
+
+ clk_free(&clk);
+ return ret;
+}
+
void board_init_f(ulong dummy)
{
struct udevice *pinctrl, *dev;
@@ -144,6 +166,8 @@ void board_init_f(ulong dummy)
return;
}
+ setup_arm_clock();
+
#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
back_to_bootrom();
#endif
--
2.39.5