From 806a5a3958e4af483e529cf0db75464055d6e13a Mon Sep 17 00:00:00 2001 From: Heiko Schocher <hs@denx.de> Date: Wed, 17 Aug 2016 09:13:24 +0200 Subject: [PATCH] ARM: at91: clock: correct PRES offset for at91sam9x5 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit on at91sam9x5 PRES offset is 4 in the PMC master clock register. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Andreas BieÃmann <andreas@biessmann.org> --- arch/arm/mach-at91/arm926ejs/clock.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-at91/arm926ejs/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c index c8d24ae826..e3181fab84 100644 --- a/arch/arm/mach-at91/arm926ejs/clock.c +++ b/arch/arm/mach-at91/arm926ejs/clock.c @@ -162,7 +162,13 @@ int at91_clock_init(unsigned long main_clock) gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); freq = gd->arch.mck_rate_hz; +#if defined(CONFIG_AT91SAM9X5) + /* different in prescale on at91sam9x5 */ + freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 4)); +#else freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ +#endif + #if defined(CONFIG_AT91SAM9G20) /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ? -- 2.39.5