From ae625ae5a14f63400b8e5ee901a27248037a2339 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Tue, 2 May 2017 20:27:41 +0200
Subject: [PATCH] ARM: at91: ma5d4: Switch DDR2 controller to sequencial
 address decoding
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According to the datasheet, sequential mapping is used for DDR
SDRAM, while interleaved mapping is used for regular SDRAM.
Incorrect configuration of this bit does indeed cause sporadic
memory instability.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Wenyou Yang <wenyou.yang@atmel.com>
---
 board/aries/ma5d4evk/ma5d4evk.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/board/aries/ma5d4evk/ma5d4evk.c b/board/aries/ma5d4evk/ma5d4evk.c
index 81463712fa..dd74e29b8e 100644
--- a/board/aries/ma5d4evk/ma5d4evk.c
+++ b/board/aries/ma5d4evk/ma5d4evk.c
@@ -349,7 +349,6 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
 		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
 		    ATMEL_MPDDRC_CR_NB_8BANKS |
 		    ATMEL_MPDDRC_CR_NDQS_DISABLED |
-		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
 		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
 
 	ddr2->rtr = 0x2b0;
-- 
2.39.5