From 3b320106917313a450f5a6a9ab3eb9aaf533bacf Mon Sep 17 00:00:00 2001
From: Ye Li <ye.li@nxp.com>
Date: Fri, 29 Oct 2021 09:46:27 +0800
Subject: [PATCH] imx8ulp: clock: Support to reset DCNano and MIPI DSI
When LPAV is allocated to RTD, the LPAV won't be reset. So we have to
reset DCNano and MIPI DSI in u-boot before enabling the drivers
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-imx8ulp/clock.h | 1 +
arch/arm/mach-imx/imx8ulp/clock.c | 8 ++++++++
2 files changed, 9 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx8ulp/clock.h b/arch/arm/include/asm/arch-imx8ulp/clock.h
index 24322f3ab2..cc70284f55 100644
--- a/arch/arm/include/asm/arch-imx8ulp/clock.h
+++ b/arch/arm/include/asm/arch-imx8ulp/clock.h
@@ -39,5 +39,6 @@ int set_ddr_clk(u32 phy_freq_mhz);
void clock_init(void);
void cgc1_enet_stamp_sel(u32 clk_src);
void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz);
+void reset_lcdclk(void);
void enable_mipi_dsi_clk(unsigned char enable);
#endif
diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c
index f54fc25763..d03269ac04 100644
--- a/arch/arm/mach-imx/imx8ulp/clock.c
+++ b/arch/arm/mach-imx/imx8ulp/clock.c
@@ -330,6 +330,7 @@ void enable_mipi_dsi_clk(unsigned char enable)
{
if (enable) {
pcc_clock_enable(5, DSI_PCC5_SLOT, false);
+ pcc_reset_peripheral(5, DSI_PCC5_SLOT, true);
pcc_clock_sel(5, DSI_PCC5_SLOT, PLL4_PFD3_DIV2);
pcc_clock_div_config(5, DSI_PCC5_SLOT, 0, 6);
pcc_clock_enable(5, DSI_PCC5_SLOT, true);
@@ -340,6 +341,13 @@ void enable_mipi_dsi_clk(unsigned char enable)
}
}
+void reset_lcdclk(void)
+{
+ /* Disable clock and reset dcnano*/
+ pcc_clock_enable(5, DCNANO_PCC5_SLOT, false);
+ pcc_reset_peripheral(5, DCNANO_PCC5_SLOT, true);
+}
+
void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz)
{
u8 pcd, best_pcd = 0;
--
2.39.5