From 21d5d5e55be85d70c06c5bad0139837665ed4699 Mon Sep 17 00:00:00 2001 From: Jacky Chou <jacky_chou@aspeedtech.com> Date: Thu, 27 Jun 2024 14:26:00 +0800 Subject: [PATCH] net: ftgmac100: Fixed the cache coherency issues of rx memory When executing TFTP, the ARP will be replied to after receiving the ARP. U-boot's ARP routine modifies the data in the receive packet in response to the ARP packet and then copies it into the transmit packet. At this point, the received packet cache is inconsistent. It is possible that the cache will perform a writeback action to affect the MAC receiving packets. Avoid the same problem that occurs in other networking protocols. In the free_pkt function, ensure cache and memory consistency. Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com> Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com> --- drivers/net/ftgmac100.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index 8781e50a48..853a9913d2 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -410,6 +410,14 @@ static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length) ulong des_end = des_start + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); + /* + * Make sure there are no stale data in write-back over this area, which + * might get written into the memory while the ftgmac100 also writes + * into the same memory area. + */ + flush_dcache_range((ulong)net_rx_packets[priv->rx_index], + (ulong)net_rx_packets[priv->rx_index] + PKTSIZE_ALIGN); + /* Release buffer to DMA and flush descriptor */ curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY; flush_dcache_range(des_start, des_end); -- 2.39.5