From: Zhichun Hua <zhichun.hua@freescale.com>
Date: Mon, 29 Jun 2015 07:49:37 +0000 (+0800)
Subject: armv8: Fix TCR macros for shareability attribute
X-Git-Tag: v2025.01-rc5-pxa1908~12597^2~1
X-Git-Url: http://git.dujemihanovic.xyz/img/html/static/gitweb.css?a=commitdiff_plain;h=21a257b9b3b29ddb1445fdafe12e05727080a198;p=u-boot.git

armv8: Fix TCR macros for shareability attribute

For ARMv8, outer shareable is 0b10, inner shareable is 0b11 at bit
position [13:12] of TCR_ELx register.

Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
---

diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 4b9cb52965..04fa0be64c 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -93,8 +93,8 @@
 #define TCR_ORGN_WBNWA		(3 << 10)
 #define TCR_ORGN_MASK		(3 << 10)
 #define TCR_SHARED_NON		(0 << 12)
-#define TCR_SHARED_OUTER	(1 << 12)
-#define TCR_SHARED_INNER	(2 << 12)
+#define TCR_SHARED_OUTER	(2 << 12)
+#define TCR_SHARED_INNER	(3 << 12)
 #define TCR_TG0_4K		(0 << 14)
 #define TCR_TG0_64K		(1 << 14)
 #define TCR_TG0_16K		(2 << 14)