From 8a204312abad7913f9b2209a71bef81853647b21 Mon Sep 17 00:00:00 2001 From: Ley Foon Tan <ley.foon.tan@intel.com> Date: Thu, 25 Jun 2020 19:19:09 +0800 Subject: [PATCH] arm: socfpga: misc_s10: Fix EMAC register address calculation Fix EMAC register address calculation, address need to multiply with sizeof(u32) or 4. This fixes write to invalid address. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> --- arch/arm/mach-socfpga/misc_s10.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c index ccff78a230..670bfa1a31 100644 --- a/arch/arm/mach-socfpga/misc_s10.c +++ b/arch/arm/mach-socfpga/misc_s10.c @@ -68,7 +68,7 @@ static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode) return -EINVAL; clrsetbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0 + - gmac_index, + (gmac_index * sizeof(u32)), SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg); return 0; -- 2.39.5