From 2ac06f3e66c13b793f9b0859888b7062f24910e6 Mon Sep 17 00:00:00 2001
From: =?utf8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
Date: Tue, 21 Dec 2021 12:20:12 +0100
Subject: [PATCH] board: gdsys: a38x: Enable PCIe link 2 in spl_board_init()
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A385 controlcenterdc board does not use PCI DM properly and touches some
PCIe devices directly in its board code.
This controlcenterdc spl_board_init() function expects that PCIe link is
already initialized. Link itself is initialized in a38x serdes code but
this will change in future and link initialization will be postponed from
U-Boot SPL to proper U-Boot.
So explicitly enable PCIe link 2 in spl_board_init() function via
SoC Control Register 1 to not break this code by future changes. This board
has PCIe link 2 just x1, so no additional initialization (except enabling
PCIe port) is needed.
Signed-off-by: Pali Rohár <pali@kernel.org>
---
board/gdsys/a38x/controlcenterdc.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c
index 243d022326..7d65400ccb 100644
--- a/board/gdsys/a38x/controlcenterdc.c
+++ b/board/gdsys/a38x/controlcenterdc.c
@@ -100,6 +100,10 @@ void spl_board_init(void)
uint k;
struct gpio_desc gpio = {};
+ /* Enable PCIe link 2 */
+ setbits_32(MVEBU_REGISTER(0x18204), BIT(2));
+ mdelay(10);
+
if (!request_gpio_by_name(&gpio, "pca9698@22", 31, "fpga-program-gpio")) {
/* prepare FPGA reconfiguration */
dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
--
2.39.5