From 193a1e9f196b7fb7e913a70936c8a49060a1859c Mon Sep 17 00:00:00 2001
From: =?utf8?q?Marek=20Beh=C3=BAn?= <marek.behun@nic.cz>
Date: Wed, 7 Aug 2019 15:01:56 +0200
Subject: [PATCH] pci: pci_mvebu: set BAR0 after memory space is set
MIME-Version: 1.0
Content-Type: text/plain; charset=utf8
Content-Transfer-Encoding: 8bit

The non-DM version of this driver used to set BAR0 register after the
calls to pci_set_region.
I found out that for some strange reason the ath10k driver in kernel
fails to work if this is done the other way around.
I know that Linux's driver should not depend on how U-Boot does things,
but for some strange reason it does and this seems to be the simplest
solution. Fix it since it caused regressions on Omnia.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Phil Sutter <phil@nwl.cc>
Cc: VlaoMao <vlaomao@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 drivers/pci/pci_mvebu.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
index e21dc10c2f..f9b08f38a1 100644
--- a/drivers/pci/pci_mvebu.c
+++ b/drivers/pci/pci_mvebu.c
@@ -313,10 +313,6 @@ static int mvebu_pcie_probe(struct udevice *dev)
 	reg |= BIT(10);		/* disable interrupts */
 	writel(reg, pcie->base + PCIE_CMD_OFF);
 
-	/* Set BAR0 to internal registers */
-	writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
-	writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
-
 	/* PCI memory space */
 	pci_set_region(hose->regions + 0, pcie->mem.start,
 		       pcie->mem.start, PCIE_MEM_SIZE, PCI_REGION_MEM);
@@ -326,6 +322,10 @@ static int mvebu_pcie_probe(struct udevice *dev)
 		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 	hose->region_count = 2;
 
+	/* Set BAR0 to internal registers */
+	writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
+	writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
+
 	bus++;
 
 	return 0;
-- 
2.39.5