From 117029c510c75f4c6d7ecb1172635d6a08755cf8 Mon Sep 17 00:00:00 2001
From: Phil Edworthy <PHIL.EDWORTHY@renesas.com>
Date: Mon, 13 Feb 2012 02:03:50 +0000
Subject: [PATCH] sh: Fix sh7264 clock speed and related serial setting

The generalised calculation of the serial bit rate reg also applies
to sh7264, it was just the clock speed that was set incorrectly.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
 drivers/serial/serial_sh.h | 2 --
 include/configs/rsk7264.h  | 2 +-
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index 4e16e4803c..0b3e779c8e 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -686,8 +686,6 @@ static inline int scbrr_calc(struct uart_port port, int bps, int clk)
 #define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk)
 #elif defined(__H8300H__) || defined(__H8300S__)
 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
-#elif defined(CONFIG_CPU_SH7264)
-#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps))
 #else /* Generic SH */
 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
 #endif
diff --git a/include/configs/rsk7264.h b/include/configs/rsk7264.h
index c1ffc348f7..af9524e8bf 100644
--- a/include/configs/rsk7264.h
+++ b/include/configs/rsk7264.h
@@ -65,7 +65,7 @@
 #define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
 
 /* Board Clock */
-#define CONFIG_SYS_CLK_FREQ	33333333
+#define CONFIG_SYS_CLK_FREQ	36000000
 #define CMT_CLK_DIVIDER		32	/* 8 (default), 32, 128 or 512 */
 #define CONFIG_SYS_HZ		(CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
 
-- 
2.39.5