From: Tom Rini <trini@ti.com>
Date: Thu, 13 Jun 2013 19:16:15 +0000 (-0400)
Subject: Merge branch 'master' of git://git.denx.de/u-boot-arm
X-Git-Tag: v2025.01-rc5-pxa1908~16183
X-Git-Url: http://git.dujemihanovic.xyz/img/html/static/git-logo.png?a=commitdiff_plain;h=41341221d12341a2ecfb280142d6478071738fc2;p=u-boot.git

Merge branch 'master' of git://git.denx.de/u-boot-arm

Small conflict over DRA7XX updates and adding SRAM_SCRATCH_SPACE_ADDR

Conflicts:
	arch/arm/include/asm/arch-omap5/omap.h

Signed-off-by: Tom Rini <trini@ti.com>
---

41341221d12341a2ecfb280142d6478071738fc2
diff --cc arch/arm/include/asm/arch-omap4/omap.h
index 44353a43f2,66afd92492..9fd00ff2aa
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@@ -141,7 -127,14 +127,15 @@@ struct s32ktimer 
   */
  #define NON_SECURE_SRAM_START	0x40304000
  #define NON_SECURE_SRAM_END	0x4030E000	/* Not inclusive */
 +#define SRAM_SCRATCH_SPACE_ADDR	NON_SECURE_SRAM_START
  /* base address for indirect vectors (internal boot mode) */
  #define SRAM_ROM_VECT_BASE	0x4030D000
+ 
+ /* ABB settings */
+ #define OMAP_ABB_SETTLING_TIME		50
+ #define OMAP_ABB_CLOCK_CYCLES		16
+ 
+ /* ABB tranxdone mask */
+ #define OMAP_ABB_MPU_TXDONE_MASK	(0x1 << 7)
+ 
  #endif
diff --cc arch/arm/include/asm/arch-omap5/omap.h
index 04af227e02,817c1ff27f..5e6d82e51f
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@@ -181,14 -169,14 +169,15 @@@ struct s32ktimer 
  #define EFUSE_4 0x45145100
  #endif /* __ASSEMBLY__ */
  
- /*
-  * Non-secure SRAM Addresses
-  * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
-  * at 0x40304000(EMU base) so that our code works for both EMU and GP
-  */
+ #ifdef CONFIG_DRA7XX
+ #define NON_SECURE_SRAM_START	0x40300000
+ #define NON_SECURE_SRAM_END	0x40380000	/* Not inclusive */
+ #else
  #define NON_SECURE_SRAM_START	0x40300000
  #define NON_SECURE_SRAM_END	0x40320000	/* Not inclusive */
+ #endif
 +#define SRAM_SCRATCH_SPACE_ADDR	NON_SECURE_SRAM_START
+ 
  /* base address for indirect vectors (internal boot mode) */
  #define SRAM_ROM_VECT_BASE	0x4031F000