From d7a1ff40d6006c818c9e74d3e13bec008638349f Mon Sep 17 00:00:00 2001 From: Chee Hong Ang <chee.hong.ang@intel.com> Date: Wed, 5 Aug 2020 21:15:56 +0800 Subject: [PATCH] arm: socfpga: soc64: Add SDM triggered warm reset bit mask Include SDM triggered warm reset bit (BIT1) in Reset Manager's stat register when checking for HPS warm reset status. Refactor the warm reset mask macro for clarity purpose. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> --- .../mach-socfpga/include/mach/reset_manager_soc64.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h index 3f952bcc6e..fc60f6a105 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h @@ -21,8 +21,15 @@ void socfpga_bridges_reset(int enable); #define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040 #define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004 -/* Watchdogs and MPU warm reset mask */ -#define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00 +/* SDM, Watchdogs and MPU warm reset mask */ +#define RSTMGR_STAT_SDMWARMRST BIT(1) +#define RSTMGR_STAT_MPU0RST_BITPOS 8 +#define RSTMGR_STAT_L4WD0RST_BITPOS 16 +#define RSTMGR_L4WD_MPU_WARMRESET_MASK (RSTMGR_STAT_SDMWARMRST | \ + GENMASK(RSTMGR_STAT_MPU0RST_BITPOS + 3, \ + RSTMGR_STAT_MPU0RST_BITPOS) | \ + GENMASK(RSTMGR_STAT_L4WD0RST_BITPOS + 3, \ + RSTMGR_STAT_L4WD0RST_BITPOS)) /* * SocFPGA Stratix10 reset IDs, bank mapping is as follows: -- 2.39.5