From 5c053f3adc69eaf83645b5d44c6adbb2d49a3fa7 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 4 Feb 2024 20:53:07 +0000
Subject: [PATCH] mmc: rockchip_sdhci: Fix HS400 mode write on RK3568
Testing has shown that writing to eMMC using HS400 modes on RK3568
result in an ERROR.
Change the tap number for transmit clock to fix this.
Also stop DLL when config_dll() is called to disable DLL.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
drivers/mmc/rockchip_sdhci.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index 285332d9f4..706fb12357 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -71,7 +71,6 @@
#define DLL_RXCLK_NO_INVERTER BIT(29)
#define DLL_RXCLK_ORI_GATE BIT(31)
#define DLL_TXCLK_TAPNUM_DEFAULT 0x10
-#define DLL_TXCLK_TAPNUM_90_DEGREES 0x9
#define DLL_TXCLK_TAPNUM_FROM_SW BIT(24)
#define DLL_TXCLK_NO_INVERTER BIT(29)
#define DLL_STRBIN_TAPNUM_DEFAULT 0x4
@@ -314,8 +313,10 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enab
int val, ret;
u32 extra, txclk_tapnum;
- if (!enable)
+ if (!enable) {
+ sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
return 0;
+ }
if (clock >= 100 * MHz) {
/* reset DLL */
@@ -648,7 +649,7 @@ static const struct sdhci_data rk3568_data = {
.config_dll = rk3568_sdhci_config_dll,
.flags = FLAG_INVERTER_FLAG_IN_RXCLK,
.hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT,
- .hs400_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT,
+ .hs400_txclk_tapnum = 0x8,
};
static const struct sdhci_data rk3588_data = {
@@ -656,7 +657,7 @@ static const struct sdhci_data rk3588_data = {
.set_clock = rk3568_sdhci_set_clock,
.config_dll = rk3568_sdhci_config_dll,
.hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT,
- .hs400_txclk_tapnum = DLL_TXCLK_TAPNUM_90_DEGREES,
+ .hs400_txclk_tapnum = 0x9,
};
static const struct udevice_id sdhci_ids[] = {
--
2.39.5