From: Tom Rini <trini@konsulko.com>
Date: Sat, 12 Nov 2022 22:36:42 +0000 (-0500)
Subject: Convert CONFIG_SYS_NAND_DBW_8 et al to Kconfig
X-Git-Tag: v2025.01-rc5-pxa1908~1158^2~14^2~64
X-Git-Url: http://git.dujemihanovic.xyz/img/html/static/git-favicon.png?a=commitdiff_plain;h=715cce65b889214a728dd44759204316aff29006;p=u-boot.git

Convert CONFIG_SYS_NAND_DBW_8 et al to Kconfig

This converts the following to Kconfig:
   CONFIG_SYS_NAND_DBW_8
   CONFIG_SYS_NAND_DBW_16

Note that all instances of the code check for CONFIG_SYS_NAND_DBW_16
being defined, and then "else" to CONFIG_SYS_NAND_DBW_8 whereas all of
the configs set CONFIG_SYS_NAND_DBW_8. So we introduce
CONFIG_SYS_NAND_DBW_16 as an option.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---

diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index da2c5795bc..48a7507c64 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -83,6 +83,18 @@ config SPL_GENERATE_ATMEL_PMECC_HEADER
 	help
 	  Generate Programmable Multibit ECC (PMECC) header for SPL image.
 
+choice
+	prompt "NAND bus width (bits)"
+	default SYS_NAND_DBW_8
+
+config SYS_NAND_DBW_8
+	bool "NAND bus width is 8 bits"
+
+config SYS_NAND_DBW_16
+	bool "NAND bus width is 16 bits"
+
+endchoice
+
 endif
 
 config NAND_BRCMNAND
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index d51da9d506..60b47379e5 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -44,7 +44,6 @@
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
 #define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
 #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
 #define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
index 5dc8f21a85..d80a686e9e 100644
--- a/include/configs/at91sam9261ek.h
+++ b/include/configs/at91sam9261ek.h
@@ -25,7 +25,6 @@
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
 #define CONFIG_SYS_NAND_BASE			0x40000000
-#define CONFIG_SYS_NAND_DBW_8
 /* our ALE is AD22 */
 #define CONFIG_SYS_NAND_MASK_ALE		(1 << 22)
 /* our CLE is AD21 */
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index d31a7742a1..89a8e43e1e 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -151,7 +151,6 @@
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
 #define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8			1
 /* our ALE is AD21 */
 #define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
 /* our CLE is AD22 */
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index 01085476a4..55edd706ea 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -21,7 +21,6 @@
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
 #define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
 /* our ALE is AD21 */
 #define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
 /* our CLE is AD22 */
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index c60c248b74..0a512c217f 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -26,7 +26,6 @@
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
 #define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8			1
 /* our ALE is AD21 */
 #define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
 /* our CLE is AD22 */
diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
index 71a2863bfc..b8a14d571d 100644
--- a/include/configs/at91sam9x5ek.h
+++ b/include/configs/at91sam9x5ek.h
@@ -28,7 +28,6 @@
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
 #define CONFIG_SYS_NAND_BASE		0x40000000
-#define CONFIG_SYS_NAND_DBW_8		1
 /* our ALE is AD21 */
 #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index 0596afbf9f..3e7c0c0d88 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -38,7 +38,6 @@
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
 #define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
 /* our ALE is AD21 */
 #define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
 /* our CLE is AD22 */
diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
index 22647abee0..a18920d3f0 100644
--- a/include/configs/ethernut5.h
+++ b/include/configs/ethernut5.h
@@ -38,7 +38,6 @@
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
 #define CONFIG_SYS_NAND_BASE		0x40000000
-#define CONFIG_SYS_NAND_DBW_8
 /* our ALE is AD21 */
 #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h
index 52b9fe2b17..3d62efb38f 100644
--- a/include/configs/gardena-smart-gateway-at91sam.h
+++ b/include/configs/gardena-smart-gateway-at91sam.h
@@ -23,7 +23,6 @@
 
 /* NAND flash */
 #define CONFIG_SYS_NAND_BASE		0x40000000
-#define CONFIG_SYS_NAND_DBW_8		1
 /* our ALE is AD21 */
 #define CONFIG_SYS_NAND_MASK_ALE	BIT(21)
 /* our CLE is AD22 */
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index 9f913fad16..30267e29a1 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -53,7 +53,6 @@
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
 # define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3 /* 0x40000000 */
-# define CONFIG_SYS_NAND_DBW_8
 # define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
 # define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
 # define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PD(15)
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index 278f1b5cc6..6a89fb1fa9 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -130,7 +130,6 @@
 
 /* NAND flash */
 #define CONFIG_SYS_NAND_BASE			0x40000000
-#define CONFIG_SYS_NAND_DBW_8			1
 /* our ALE is AD22 */
 #define CONFIG_SYS_NAND_MASK_ALE		(1 << 22)
 /* our CLE is AD21 */
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index 7c23206a30..c56db4d793 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -147,7 +147,6 @@
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
 #define CONFIG_SYS_NAND_BASE		0x40000000
-#define CONFIG_SYS_NAND_DBW_8		1
 /* our ALE is AD21 */
 #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
index 35fd525683..7d3a326dea 100644
--- a/include/configs/pm9g45.h
+++ b/include/configs/pm9g45.h
@@ -26,7 +26,6 @@
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
 #define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
 /* our ALE is AD21 */
 #define CONFIG_SYS_NAND_MASK_ALE		BIT(21)
 /* our CLE is AD22 */
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index a77215d19b..c8f5816fed 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -55,7 +55,6 @@
 
 /* NAND flash settings */
 #define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
 #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
 #define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h
index c56fb37831..6aba1d3194 100644
--- a/include/configs/snapper9g45.h
+++ b/include/configs/snapper9g45.h
@@ -31,7 +31,6 @@
 /* NAND Flash */
 #define CONFIG_SYS_NAND_ECC_BASE	ATMEL_BASE_ECC
 #define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
 #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21) /* AD21 */
 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22) /* AD22 */
 #define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index 45780d9a4e..ca9616d8af 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -55,7 +55,6 @@
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
 #define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
 #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
 #define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14