From: Aneesh Bansal <aneesh.bansal@freescale.com>
Date: Wed, 14 May 2014 06:15:15 +0000 (+0530)
Subject: powerpc/mpc85xx: SECURE BOOT- corrected CSPR settings for BSC9132QDS NAND
X-Git-Tag: v2025.01-rc5-pxa1908~15317^2~3
X-Git-Url: http://git.dujemihanovic.xyz/img/html/static/git-favicon.png?a=commitdiff_plain;h=3051f3f999cc1bae465126f5766329058e12acfa;p=u-boot.git

powerpc/mpc85xx: SECURE BOOT- corrected CSPR settings for BSC9132QDS NAND

In case of secure boot from NAND, CSPR and FTIM settings are
same as non-secure NAND boot. CSPR0 is configured as NAND and
CSPR1 is configured as NOR.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
---

diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index e76a04b262..7bb5d33d0c 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -360,7 +360,7 @@ combinations. this should be removed later
 #endif
 
 /* Set up IFC registers for boot location NOR/NAND */
-#if defined(CONFIG_NAND)
+#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR