From d46ec0bbaf1a38711b493266f49bb26ac9157d8a Mon Sep 17 00:00:00 2001
From: York Sun <york.sun@nxp.com>
Date: Mon, 29 Jan 2018 09:44:34 -0800
Subject: [PATCH] drivers/ddr/fsl: Fix workaround for A009803
Wrong field was masked in this workaround due to wrong endianness. The
impacted SoCs have big-endian.
Signed-off-by: York Sun <york.sun@nxp.com>
---
drivers/ddr/fsl/fsl_ddr_gen4.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index b3a27ec5a8..7df9178415 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -210,7 +210,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
ddr_out32(&ddr->ddr_sdram_rcw_2,
- regs->ddr_sdram_rcw_2 & ~0x0f000000);
+ regs->ddr_sdram_rcw_2 & ~0xf0);
}
ddr_out32(&ddr->err_disable, regs->err_disable |
DDR_ERR_DISABLE_APED);
--
2.39.5