From: Prabhakar Kushwaha <prabhakar@freescale.com>
Date: Wed, 11 Dec 2013 07:19:13 +0000 (+0530)
Subject: powerpc/mpc85xx: Update CONFIG_SYS_FSL_TBCLK_DIV for T1040
X-Git-Tag: v2025.01-rc5-pxa1908~15510^2~80
X-Git-Url: http://git.dujemihanovic.xyz/img/html/index.html?a=commitdiff_plain;h=e03c76c30342797a25ef9350e51c8daa0b56f1df;p=u-boot.git

powerpc/mpc85xx: Update CONFIG_SYS_FSL_TBCLK_DIV for T1040

The default value of CONFIG_SYS_FSL_TBCLK_DIV is 16.

So, update its value as default.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
---

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 99e16bdf63..244ccbf24f 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -711,7 +711,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define CONFIG_FM_PLAT_CLK_DIV	1
 #define CONFIG_SYS_FM1_CLK		CONFIG_FM_PLAT_CLK_DIV
 #define CONFIG_SYS_FM_MURAM_SIZE	0x30000
-#define CONFIG_SYS_FSL_TBCLK_DIV	32
+#define CONFIG_SYS_FSL_TBCLK_DIV	16
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE