From: York Sun <yorksun@freescale.com>
Date: Fri, 5 Sep 2014 05:52:42 +0000 (+0800)
Subject: driver/ddr/freescale: Fix DDR3 driver for ARM
X-Git-Tag: v2025.01-rc5-pxa1908~14703^2~8
X-Git-Url: http://git.dujemihanovic.xyz/img/html/index.html?a=commitdiff_plain;h=5cb27c5d44ac789f0f0583b57c15dc708ca55c69;p=u-boot.git

driver/ddr/freescale: Fix DDR3 driver for ARM

Reading DDR register should use ddr_in32() for proper endianess.
This patch fixes incorrect waiting time for ARM platforms.

Signed-off-by: York Sun <yorksun@freescale.com>
---

diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c
index d4ed9aec2a..59f2fd6610 100644
--- a/drivers/ddr/fsl/arm_ddr_gen3.c
+++ b/drivers/ddr/fsl/arm_ddr_gen3.c
@@ -194,7 +194,7 @@ step2:
 	 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
 	 * Let's wait for 800ms
 	 */
-	bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
+	bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
 			>> SDRAM_CFG_DBW_SHIFT);
 	timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
 		(get_ddr_freq(0) >> 20)) << 1;