From: Ley Foon Tan <ley.foon.tan@intel.com>
Date: Wed, 15 Aug 2018 18:20:17 +0000 (+0800)
Subject: arm: socfpga: Fix SYSMGR_FPGAINTF_EMACx bit mask
X-Git-Tag: v2025.01-rc5-pxa1908~3730^2
X-Git-Url: http://git.dujemihanovic.xyz/img/html/%7B%7B%20%28.OutputFormats.Get?a=commitdiff_plain;h=b0c0a715f90690a7dd4f33cb5b5c21960be26d3c;p=u-boot.git

arm: socfpga: Fix SYSMGR_FPGAINTF_EMACx bit mask

Bitmask for EMAC should be bit-0, EMAC1 bit-8 and EMAC2 bit-16.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
index 813dff2153..297f9e1999 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
@@ -146,9 +146,9 @@ struct socfpga_system_manager {
 #define SYSMGR_FPGAINTF_SDMMC	BIT(8)
 #define SYSMGR_FPGAINTF_SPIM0	BIT(16)
 #define SYSMGR_FPGAINTF_SPIM1	BIT(24)
-#define SYSMGR_FPGAINTF_EMAC0	(0x11 << 0)
-#define SYSMGR_FPGAINTF_EMAC1	(0x11 << 8)
-#define SYSMGR_FPGAINTF_EMAC2	(0x11 << 16)
+#define SYSMGR_FPGAINTF_EMAC0	BIT(0)
+#define SYSMGR_FPGAINTF_EMAC1	BIT(8)
+#define SYSMGR_FPGAINTF_EMAC2	BIT(16)
 
 #define SYSMGR_SDMMC_SMPLSEL_SHIFT	4
 #define SYSMGR_SDMMC_DRVSEL_SHIFT	0