From 0ee84b88b78bce425190d8cd7adf4c30cba0c2f0 Mon Sep 17 00:00:00 2001
From: Ed Swarthout <Ed.Swarthout@freescale.com>
Date: Tue, 24 Feb 2009 02:37:59 -0600
Subject: [PATCH] Fix mpc85xx ddr-gen3 ddr_sdram_cfg.

Commit e1be0d25, "32bit BUg fix for DDR2 on 8572" prevented other
sdram_cfg bits (such as ecc and self_refresh_in_sleep) from being set.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
---
 cpu/mpc85xx/ddr-gen3.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/cpu/mpc85xx/ddr-gen3.c b/cpu/mpc85xx/ddr-gen3.c
index 8dc2b3ac52..99c325a4ff 100644
--- a/cpu/mpc85xx/ddr-gen3.c
+++ b/cpu/mpc85xx/ddr-gen3.c
@@ -79,8 +79,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 	out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 
-	/* Do not enable the memory */
-	temp_sdram_cfg = in_be32(&ddr->sdram_cfg);
+	/* Set, but do not enable the memory */
+	temp_sdram_cfg = regs->ddr_sdram_cfg;
 	temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
 	out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 	/*
-- 
2.39.5