From: Ken Ma <make@marvell.com>
Date: Mon, 26 Mar 2018 07:56:00 +0000 (+0800)
Subject: arm64: a37xx: dts: Fix the number of GPIO on south bridge
X-Git-Tag: v2025.01-rc5-pxa1908~4620^2~12
X-Git-Url: http://git.dujemihanovic.xyz/img/%7B%7B?a=commitdiff_plain;h=8aecbcd166d8ce81556e9bb4ab6b160f18a524d1;p=u-boot.git
arm64: a37xx: dts: Fix the number of GPIO on south bridge
The number of pins in South Bridge is 30 and not 29. There is a fix for
the driver for the pinctrl, but a fix is also need at device tree level
for the GPIO.
Reviewed-on: http://vgitil04.il.marvell.com:8080/43286
Reviewed-by: Hua Jing <jinghua@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi
index fab95bbc12..d139a617a9 100644
--- a/arch/arm/dts/armada-37xx.dtsi
+++ b/arch/arm/dts/armada-37xx.dtsi
@@ -168,7 +168,7 @@
reg = <0x18800 0x100>, <0x18C00 0x20>;
gpiosb: gpiosb {
#gpio-cells = <2>;
- gpio-ranges = <&pinctrl_sb 0 0 29>;
+ gpio-ranges = <&pinctrl_sb 0 0 30>;
gpio-controller;
interrupts =
<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,