From: Wadim Egorov <w.egorov@phytec.de>
Date: Mon, 10 Jun 2024 13:33:52 +0000 (+0200)
Subject: board: phytec: phycore-am62x: Use memory nodes in higher boot stages
X-Git-Url: http://git.dujemihanovic.xyz/img/%7B%7B?a=commitdiff_plain;h=680fcbcf55064c5cdf3ef653209da0e925adade6;p=u-boot.git

board: phytec: phycore-am62x: Use memory nodes in higher boot stages

There is no need to reread the EEPROM multiple times in different stages
to detect the RAM size. We can do this once at an early stage and let
higher stages decode memory nodes using fdtdec.
Make sure to pass fixup memory nodes before passing to u-boot stage.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Daniel Schultz <d.schultz@phytec.de>
---

diff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c
index 35e1bb96b8..9f6bc736cb 100644
--- a/board/phytec/phycore_am62x/phycore-am62x.c
+++ b/board/phytec/phycore_am62x/phycore-am62x.c
@@ -47,7 +47,12 @@ static u8 phytec_get_am62_ddr_size_default(void)
 
 int dram_init(void)
 {
-	u8 ram_size = phytec_get_am62_ddr_size_default();
+	u8 ram_size;
+
+	if (!IS_ENABLED(CONFIG_CPU_V7R))
+		return fdtdec_setup_mem_size_base();
+
+	ram_size = phytec_get_am62_ddr_size_default();
 
 	/*
 	 * HACK: ddrss driver support 2GB RAM by default
@@ -92,6 +97,9 @@ int dram_init_banksize(void)
 {
 	u8 ram_size;
 
+	if (!IS_ENABLED(CONFIG_CPU_V7R))
+		return fdtdec_setup_memory_banksize();
+
 	ram_size = phytec_get_am62_ddr_size_default();
 	switch (ram_size) {
 	case EEPROM_RAM_SIZE_1GB:
@@ -174,6 +182,26 @@ int do_board_detect(void)
 }
 #endif
 
+#if IS_ENABLED(CONFIG_SPL_BUILD)
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+	u64 start[CONFIG_NR_DRAM_BANKS];
+	u64 size[CONFIG_NR_DRAM_BANKS];
+	int bank;
+	int ret;
+
+	dram_init();
+	dram_init_banksize();
+
+	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+		start[bank] = gd->bd->bi_dram[bank].start;
+		size[bank] = gd->bd->bi_dram[bank].size;
+	}
+
+	ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, CONFIG_NR_DRAM_BANKS);
+}
+#endif
+
 #define CTRLMMR_USB0_PHY_CTRL   0x43004008
 #define CTRLMMR_USB1_PHY_CTRL   0x43004018
 #define CORE_VOLTAGE            0x80000000