clk: mediatek: mt7986: convert to unified infracfg gates + muxes

Convert to infracfg gates + muxes implementation now that it's
supported.

Drop infracfg-ao nodes and rename all infracfg-ao clocks to infracfg.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>

diff --git a/arch/arm/dts/mt7986.dtsi b/arch/arm/dts/mt7986.dtsi
index 187e1298fae79f10e3d561a14fb1059f979af875..a44f5386390061d61b0080416090dd537f68f610 100644 (file)
--- a/arch/arm/dts/mt7986.dtsi
+++ b/arch/arm/dts/mt7986.dtsi
@@ -115,13 +115,6 @@
                #clock-cells = <1>;
        };
 
-       infracfg_ao: infracfg_ao@10001000 {
-               compatible = "mediatek,mt7986-infracfg_ao";
-               reg = <0x10001000 0x68>;
-               clock-parent = <&infracfg>;
-               #clock-cells = <1>;
-       };
-
        infracfg: infracfg@10001040 {
                compatible = "mediatek,mt7986-infracfg";
                reg = <0x10001000 0x1000>;
@@ -155,9 +148,9 @@
                #pwm-cells = <2>;
                interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&topckgen CK_TOP_PWM_SEL>,
-                        <&infracfg_ao CK_INFRA_PWM_BSEL>,
-                        <&infracfg_ao CK_INFRA_PWM1_CK>,
-                        <&infracfg_ao CK_INFRA_PWM2_CK>;
+                        <&infracfg CK_INFRA_PWM_BSEL>,
+                        <&infracfg CK_INFRA_PWM1_CK>,
+                        <&infracfg CK_INFRA_PWM2_CK>;
                assigned-clocks = <&topckgen CK_TOP_PWM_SEL>,
                                  <&infracfg CK_INFRA_PWM_BSEL>,
                                  <&infracfg CK_INFRA_PWM1_SEL>,
@@ -175,9 +168,9 @@
                compatible = "mediatek,hsuart";
                reg = <0x11002000 0x400>;
                interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&infracfg_ao CK_INFRA_UART0_CK>;
+               clocks = <&infracfg CK_INFRA_UART0_CK>;
                assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
-                                 <&infracfg_ao CK_INFRA_UART0_SEL>;
+                                 <&infracfg CK_INFRA_UART0_SEL>;
                assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
                                         <&topckgen CK_TOP_UART_SEL>;
                mediatek,force-highspeed;
@@ -189,7 +182,7 @@
                compatible = "mediatek,hsuart";
                reg = <0x11003000 0x400>;
                interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&infracfg_ao CK_INFRA_UART1_CK>;
+               clocks = <&infracfg CK_INFRA_UART1_CK>;
                assigned-clocks = <&infracfg CK_INFRA_UART1_SEL>;
                assigned-clock-parents = <&topckgen CK_TOP_F26M_SEL>;
                mediatek,force-highspeed;
@@ -200,7 +193,7 @@
                compatible = "mediatek,hsuart";
                reg = <0x11004000 0x400>;
                interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&infracfg_ao CK_INFRA_UART2_CK>;
+               clocks = <&infracfg CK_INFRA_UART2_CK>;
                assigned-clocks = <&infracfg CK_INFRA_UART2_SEL>;
                assigned-clock-parents = <&topckgen CK_TOP_F26M_SEL>;
                mediatek,force-highspeed;
@@ -212,9 +205,9 @@
                reg = <0x11005000 0x1000>,
                      <0x11006000 0x1000>;
                reg-names = "nfi", "ecc";
-               clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>,
-                        <&infracfg_ao CK_INFRA_NFI1_CK>,
-                        <&infracfg_ao CK_INFRA_NFI_HCK_CK>;
+               clocks = <&infracfg CK_INFRA_SPINFI1_CK>,
+                        <&infracfg CK_INFRA_NFI1_CK>,
+                        <&infracfg CK_INFRA_NFI_HCK_CK>;
                clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
                assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
                                  <&topckgen CK_TOP_NFI1X_SEL>;
@@ -258,7 +251,7 @@
        spi0: spi@1100a000 {
                compatible = "mediatek,ipm-spi";
                reg = <0x1100a000 0x100>;
-               clocks = <&infracfg_ao CK_INFRA_SPI0_CK>,
+               clocks = <&infracfg CK_INFRA_SPI0_CK>,
                         <&topckgen CK_TOP_SPI_SEL>;
                assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
                                  <&infracfg CK_INFRA_SPI0_SEL>;
@@ -283,7 +276,7 @@
                interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&topckgen CK_TOP_EMMC_416M_SEL>,
                        <&topckgen CK_TOP_EMMC_250M_SEL>,
-                       <&infracfg_ao CK_INFRA_MSDC_CK>;
+                       <&infracfg CK_INFRA_MSDC_CK>;
                assigned-clocks = <&topckgen CK_TOP_EMMC_416M_SEL>,
                                  <&topckgen CK_TOP_EMMC_250M_SEL>;
                assigned-clock-parents = <&fixed_plls CK_APMIXED_MPLL>,

diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index 59b82ca7de1a312b4cd241b385b161207d495396..b163ffc9f1a262f25caf2ce33a38ccb5b9b8eeac 100644 (file)
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -448,7 +448,7 @@ static const struct mtk_gate_regs infra_2_cg_regs = {
 
 /* INFRA GATE */
 
-static const struct mtk_gate infracfg_ao_gates[] = {
+static const struct mtk_gate infracfg_gates[] = {
        /* INFRA0 */
        GATE_INFRA0_INFRA(CK_INFRA_GPT_STA, "infra_gpt_sta", CK_INFRA_SYSAXI_D2, 0),
        GATE_INFRA0_INFRA(CK_INFRA_PWM_HCK, "infra_pwm_hck", CK_INFRA_SYSAXI_D2, 1),
@@ -536,6 +536,7 @@ static const struct mtk_clk_tree mt7986_infracfg_clk_tree = {
        .gates_offs = CK_INFRA_GPT_STA,
        .fdivs = infra_fixed_divs,
        .muxes = infra_muxes,
+       .gates = infracfg_gates,
        .flags = CLK_INFRASYS,
 };
 
@@ -590,20 +591,9 @@ static const struct udevice_id mt7986_infracfg_compat[] = {
        {}
 };
 
-static const struct udevice_id mt7986_infracfg_ao_compat[] = {
-       { .compatible = "mediatek,mt7986-infracfg_ao" },
-       {}
-};
-
 static int mt7986_infracfg_probe(struct udevice *dev)
 {
-       return mtk_common_clk_init(dev, &mt7986_infracfg_clk_tree);
-}
-
-static int mt7986_infracfg_ao_probe(struct udevice *dev)
-{
-       return mtk_common_clk_gate_init(dev, &mt7986_infracfg_clk_tree,
-                                       infracfg_ao_gates);
+       return mtk_common_clk_infrasys_init(dev, &mt7986_infracfg_clk_tree);
 }
 
 U_BOOT_DRIVER(mtk_clk_infracfg) = {
@@ -616,16 +606,6 @@ U_BOOT_DRIVER(mtk_clk_infracfg) = {
        .flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_infracfg_ao) = {
-       .name = "mt7986-clock-infracfg-ao",
-       .id = UCLASS_CLK,
-       .of_match = mt7986_infracfg_ao_compat,
-       .probe = mt7986_infracfg_ao_probe,
-       .priv_auto = sizeof(struct mtk_cg_priv),
-       .ops = &mtk_clk_gate_ops,
-       .flags = DM_FLAG_PRE_RELOC,
-};
-
 /* ethsys */
 static const struct mtk_gate_regs eth_cg_regs = {
        .sta_ofs = 0x30,