clk: mediatek: mt7622: add missing clock PERI_UART4_PD

Add missing clock PERI_UART4_PD for peri clock gates. This is needed to
match upstream linux clk ID in preparation for OF_UPSTREAM.
Also convert infracfg to mux + gate implementation as now we have mux on
top of gates.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>

diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index 0da7a8481633f6e085a183627fa82815cbb3a35f..5df62e64c9a9b55aba43eee7e2325d1c5fb5c4b2 100644 (file)
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -472,6 +472,7 @@ static const struct mtk_gate peri_cgs[] = {
        GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_AXI_SEL, 18),
        GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_AXI_SEL, 19),
        GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_AXI_SEL, 20),
+       GATE_PERI0(CLK_PERI_UART4_PD, CLK_TOP_AXI_SEL, 21),
        GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_AXI_SEL, 22),
        GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_AXI_SEL, 23),
        GATE_PERI0(CLK_PERI_I2C1_PD, CLK_TOP_AXI_SEL, 24),

diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h
index 0820fab0a22a90563d083c1922199b90bb4d4ce8..4b6501c10201006280a08a2c7ca1e440bf3335c0 100644 (file)
--- a/include/dt-bindings/clock/mt7622-clk.h
+++ b/include/dt-bindings/clock/mt7622-clk.h
@@ -146,18 +146,19 @@
 #define CLK_PERI_UART1_PD              13
 #define CLK_PERI_UART2_PD              14
 #define CLK_PERI_UART3_PD              15
-#define CLK_PERI_BTIF_PD               16
-#define CLK_PERI_I2C0_PD               17
-#define CLK_PERI_I2C1_PD               18
-#define CLK_PERI_I2C2_PD               19
-#define CLK_PERI_SPI1_PD               20
-#define CLK_PERI_AUXADC_PD             21
-#define CLK_PERI_SPI0_PD               22
-#define CLK_PERI_SNFI_PD               23
-#define CLK_PERI_NFI_PD                        24
-#define CLK_PERI_NFIECC_PD             25
-#define CLK_PERI_FLASH_PD              26
-#define CLK_PERI_IRTX_PD               27
+#define CLK_PERI_UART4_PD              16
+#define CLK_PERI_BTIF_PD               17
+#define CLK_PERI_I2C0_PD               18
+#define CLK_PERI_I2C1_PD               19
+#define CLK_PERI_I2C2_PD               20
+#define CLK_PERI_SPI1_PD               21
+#define CLK_PERI_AUXADC_PD             22
+#define CLK_PERI_SPI0_PD               23
+#define CLK_PERI_SNFI_PD               24
+#define CLK_PERI_NFI_PD                        25
+#define CLK_PERI_NFIECC_PD             26
+#define CLK_PERI_FLASH_PD              27
+#define CLK_PERI_IRTX_PD               28
 
 /* APMIXEDSYS */