From de6da9255ac4017e6bf6c98f533829a6eb67f3f6 Mon Sep 17 00:00:00 2001
From: Pavel Machek <pavel@denx.de>
Date: Tue, 9 Sep 2014 14:03:28 +0200
Subject: [PATCH] arm: socfpga: Add watchdog disable for socfpga
This adds watchdog disable. It is neccessary for running Linux kernel.
Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
V2: Move RSTMGR_PERMODRST_L4WD0_LSB to reset_manager.h
Reset watchdog only if CONFIG_HW_WATCHDOG is undefined (the default)
---
arch/arm/cpu/armv7/socfpga/misc.c | 14 ++++++++++++++
arch/arm/cpu/armv7/socfpga/reset_manager.c | 12 ++++++++++++
arch/arm/include/asm/arch-socfpga/reset_manager.h | 4 ++++
3 files changed, 30 insertions(+)
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c
index ecae393410..b633615208 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -8,6 +8,7 @@
#include <asm/io.h>
#include <miiphy.h>
#include <netdev.h>
+#include <asm/arch/reset_manager.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -36,6 +37,19 @@ int overwrite_console(void)
}
#endif
+int arch_cpu_init(void)
+{
+ /*
+ * If the HW watchdog is NOT enabled, make sure it is not running,
+ * for example because it was enabled in the preloader. This might
+ * trigger a watchdog-triggered reboot of Linux kernel later.
+ */
+#ifndef CONFIG_HW_WATCHDOG
+ socfpga_watchdog_reset();
+#endif
+ return 0;
+}
+
int misc_init_r(void)
{
return 0;
diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c
index e320c011ae..5d7aba467f 100644
--- a/arch/arm/cpu/armv7/socfpga/reset_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c
@@ -14,6 +14,18 @@ DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS;
+/* Toggle reset signal to watchdog (WDT is disabled after this operation!) */
+void socfpga_watchdog_reset(void)
+{
+ /* assert reset for watchdog */
+ setbits_le32(&reset_manager_base->per_mod_reset,
+ 1 << RSTMGR_PERMODRST_L4WD0_LSB);
+
+ /* deassert watchdog from reset (watchdog in not running state) */
+ clrbits_le32(&reset_manager_base->per_mod_reset,
+ 1 << RSTMGR_PERMODRST_L4WD0_LSB);
+}
+
/*
* Write the reset manager register to cause reset
*/
diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h
index 3e95476828..18506e69fd 100644
--- a/arch/arm/include/asm/arch-socfpga/reset_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h
@@ -10,6 +10,8 @@
void reset_cpu(ulong addr);
void reset_deassert_peripherals_handoff(void);
+void socfpga_watchdog_reset(void);
+
struct socfpga_reset_manager {
u32 status;
u32 ctrl;
@@ -27,4 +29,6 @@ struct socfpga_reset_manager {
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
#endif
+#define RSTMGR_PERMODRST_L4WD0_LSB 6
+
#endif /* _RESET_MANAGER_H_ */
--
2.39.5