From 6fbbe2d8f671920948a0b1882c6884cfdd0cbe67 Mon Sep 17 00:00:00 2001
From: Vipul Kumar <vipul.kumar@xilinx.com>
Date: Sat, 10 Mar 2018 17:52:23 +0530
Subject: [PATCH] nand: arasan_nfc: Fixed NAND write issue
In commit 2453c695185f ("arm64: zynqmp: nand: Fixed NAND erase issue for
size 1GiB or more"), ARASAN_NAND_MEM_ADDR1_PAGE_MASK macro changed
to 0xFFFF and the same macro is used in nand write and so that getting
nand write error.
This patch reverted this macro to the 0xFFFF0000 and used
ARASAN_NAND_MEM_ADDR1_COL_MASK in the nand erase function
which is equal to 0xFFFF.
Signed-off-by: Vipul Kumar <vipulk@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
drivers/mtd/nand/arasan_nfc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/arasan_nfc.c b/drivers/mtd/nand/arasan_nfc.c
index 9c82c7db33..3be66efb73 100644
--- a/drivers/mtd/nand/arasan_nfc.c
+++ b/drivers/mtd/nand/arasan_nfc.c
@@ -86,7 +86,7 @@ struct arasan_nand_command_format {
#define ARASAN_NAND_CMD_ADDR_CYCL_MASK 0x70000000
#define ARASAN_NAND_CMD_ADDR_CYCL_SHIFT 28
-#define ARASAN_NAND_MEM_ADDR1_PAGE_MASK 0xFFFF
+#define ARASAN_NAND_MEM_ADDR1_PAGE_MASK 0xFFFF0000
#define ARASAN_NAND_MEM_ADDR1_COL_MASK 0xFFFF
#define ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT 16
#define ARASAN_NAND_MEM_ADDR2_PAGE_MASK 0xFF
@@ -796,7 +796,7 @@ static int arasan_nand_erase(struct arasan_nand_command_format *curr_cmd,
writel(reg_val, &arasan_nand_base->cmd_reg);
page = (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
- ARASAN_NAND_MEM_ADDR1_PAGE_MASK;
+ ARASAN_NAND_MEM_ADDR1_COL_MASK;
column = page_addr & ARASAN_NAND_MEM_ADDR1_COL_MASK;
writel(column | (page << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT),
&arasan_nand_base->memadr_reg1);
--
2.39.5