From 2c494e62c31a34746d88511e075aa187ac3f7d10 Mon Sep 17 00:00:00 2001
From: Ley Foon Tan <ley.foon.tan@intel.com>
Date: Wed, 3 Apr 2019 13:45:02 +0800
Subject: [PATCH] arm: dts: Stratix10: Add QSPI node
Merge qspi dts node from Linux.
Commit 0cb140d07fc75fb (arm64: dts: stratix10: Add QSPI support for Stratix10)
Add -u-boot.dtsi files for non Linux dts properties and
update properties for Uboot.
- add u-boot,dm-pre-reloc
- add alias for spi0
- change compatible for flash
- support quad read and quad write
- change maximum frequency to 100MHz
Tested on Stratix 10 SoC devkit.
SOCFPGA_STRATIX10 # sf probe 0:0
SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
arch/arm/dts/socfpga_stratix10.dtsi | 13 +++++++
.../dts/socfpga_stratix10_socdk-u-boot.dtsi | 25 +++++++++++++
arch/arm/dts/socfpga_stratix10_socdk.dts | 35 +++++++++++++++++++
3 files changed, 73 insertions(+)
mode change 100644 => 100755 arch/arm/dts/socfpga_stratix10.dtsi
create mode 100755 arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
mode change 100644 => 100755 arch/arm/dts/socfpga_stratix10_socdk.dts
diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi
old mode 100644
new mode 100755
index ee93725d64..d1ae2fabae
--- a/arch/arm/dts/socfpga_stratix10.dtsi
+++ b/arch/arm/dts/socfpga_stratix10.dtsi
@@ -237,6 +237,19 @@
reg = <0xffe00000 0x100000>;
};
+ qspi: spi@ff8d2000 {
+ compatible = "cdns,qspi-nor";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xff8d2000 0x100>,
+ <0xff900000 0x100000>;
+ interrupts = <0 3 4>;
+ cdns,fifo-depth = <128>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x00000000>;
+ status = "disabled";
+ };
+
rst: rstmgr@ffd11000 {
#reset-cells = <1>;
compatible = "altr,rst-mgr";
diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
new file mode 100755
index 0000000000..e1cfb522bf
--- /dev/null
+++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+/{
+ aliases {
+ spi0 = &qspi;
+ };
+};
+
+&qspi {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+};
+
+&flash0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <100000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts
old mode 100644
new mode 100755
index c59b77d829..2745050810
--- a/arch/arm/dts/socfpga_stratix10_socdk.dts
+++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
@@ -87,6 +87,41 @@
smplsel = <0>;
};
+&qspi {
+ flash0: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q00a";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+
+ m25p,fast-read;
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ cdns,read-delay = <1>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qspi_boot: partition@0 {
+ label = "Boot and fpga data";
+ reg = <0x0 0x4000000>;
+ };
+
+ qspi_rootfs: partition@4000000 {
+ label = "Root Filesystem - JFFS2";
+ reg = <0x4000000 0x4000000>;
+ };
+ };
+ };
+};
+
&uart0 {
status = "okay";
};
--
2.39.5