From 117ef65502ccb5a5d1ee02595e94be9205b760aa Mon Sep 17 00:00:00 2001
From: =?utf8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
Date: Thu, 8 Sep 2022 16:06:50 +0200
Subject: [PATCH] arm: mvebu: Fix function enable_caches
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Commit 3308933d2fe9 ("arm: mvebu: Avoid reading MVEBU_REG_PCIE_DEVID
register too many times") broke support for caches on all Armada SoCs.
Before that commit there was code:
if (mvebu_soc_family() != MVEBU_SOC_A375) {
dcache_enable();
}
And after that commit there is code:
if (IS_ENABLED(CONFIG_ARMADA_375)) {
dcache_enable();
}
Comment above this code says that d-cache should be disabled on Armada 375.
But new code inverted logic and broke Armada 375 and slowed down all other
Armada SoCs (including A38x).
Fix this issue by changing logic to:
if (!IS_ENABLED(CONFIG_ARMADA_375)) {
dcache_enable();
}
Which matches behavior prior that commit.
Fixes: 3308933d2fe9 ("arm: mvebu: Avoid reading MVEBU_REG_PCIE_DEVID register too many times")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
---
arch/arm/mach-mvebu/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 5626b9197b..7b722ca812 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -663,7 +663,7 @@ void enable_caches(void)
* ethernet driver (mvpp2). So lets keep the d-cache disabled
* until this is solved.
*/
- if (IS_ENABLED(CONFIG_ARMADA_375)) {
+ if (!IS_ENABLED(CONFIG_ARMADA_375)) {
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
--
2.39.5