From: Igor Prusov Date: Tue, 5 Dec 2023 23:23:34 +0000 (+0300) Subject: dm: test: clk: Add test for ccf clk_set_rate() X-Git-Url: http://git.dujemihanovic.xyz/img/%7B%7B%20%28.OutputFormats.Get?a=commitdiff_plain;h=9e0250321a0d7c7b17fcbac172dd3d3c000ee53a;p=u-boot.git dm: test: clk: Add test for ccf clk_set_rate() Add a simple test case which sets clock rate to its current value. Signed-off-by: Igor Prusov Reviewed-by: Sean Anderson Link: https://lore.kernel.org/r/20231205232334.2931-3-ivprusov@salutedevices.com --- diff --git a/test/dm/clk_ccf.c b/test/dm/clk_ccf.c index e4ebb93cda..3b23982541 100644 --- a/test/dm/clk_ccf.c +++ b/test/dm/clk_ccf.c @@ -63,6 +63,9 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) rate = clk_get_parent_rate(clk); ut_asserteq(rate, 60000000); + rate = clk_set_rate(clk, 60000000); + ut_asserteq(rate, -ENOSYS); + rate = clk_get_rate(clk); ut_asserteq(rate, 60000000); @@ -87,6 +90,9 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) ut_asserteq_str("pll3_80m", pclk->dev->name); ut_asserteq(CLK_SET_RATE_PARENT, pclk->flags); + rate = clk_set_rate(clk, 80000000); + ut_asserteq(rate, -ENOSYS); + rate = clk_get_rate(clk); ut_asserteq(rate, 80000000); @@ -108,6 +114,9 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) rate = clk_get_rate(clk); ut_asserteq(rate, 60000000); + rate = clk_set_rate(clk, 60000000); + ut_asserteq(rate, 60000000); + #if CONFIG_IS_ENABLED(CLK_CCF) /* Test clk tree enable/disable */ ret = clk_get_by_id(SANDBOX_CLK_I2C_ROOT, &clk);