From 842fb5de424e53d097230a1d0ab6d7ba39b446c7 Mon Sep 17 00:00:00 2001 From: Johan Jonker <jbx6244@gmail.com> Date: Mon, 13 Mar 2023 01:32:18 +0100 Subject: [PATCH] drivers: use devfdt_get_addr_size_index_ptr when cast to pointer The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use devfdt_get_addr_size_index_ptr instead of the devfdt_get_addr_size_index function in the various files in the drivers directory that cast to a pointer. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org> --- drivers/pci/pcie_dw_mvebu.c | 6 +++--- drivers/spi/cadence_qspi.c | 3 +-- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c index a0b82c7832..3b2ada5464 100644 --- a/drivers/pci/pcie_dw_mvebu.c +++ b/drivers/pci/pcie_dw_mvebu.c @@ -569,9 +569,9 @@ static int pcie_dw_mvebu_of_to_plat(struct udevice *dev) return -EINVAL; /* Get the config space base address and size */ - pcie->cfg_base = (void *)devfdt_get_addr_size_index(dev, 1, - &pcie->cfg_size); - if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE) + pcie->cfg_base = devfdt_get_addr_size_index_ptr(dev, 1, + &pcie->cfg_size); + if (!pcie->cfg_base) return -EINVAL; return 0; diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index f931e4cf3e..ac81468a18 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -390,8 +390,7 @@ static int cadence_spi_of_to_plat(struct udevice *bus) ofnode subnode; plat->regbase = (void *)devfdt_get_addr_index(bus, 0); - plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1, - &plat->ahbsize); + plat->ahbbase = devfdt_get_addr_size_index_ptr(bus, 1, &plat->ahbsize); plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs"); plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128); plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4); -- 2.39.5