mmc: exynos_dw_mmc: Improve coding style

Fix most of checkpatch warnings and other obvious style issues.

No functional change.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/arch/arm/mach-exynos/include/mach/dwmmc.h b/arch/arm/mach-exynos/include/mach/dwmmc.h
index 7cb71be0d9fd5cbbfc03d26a6f23a7671d5fc661..75d84988b7d6e255906607a7a61cd213c2153a5a 100644 (file)
--- a/arch/arm/mach-exynos/include/mach/dwmmc.h
+++ b/arch/arm/mach-exynos/include/mach/dwmmc.h
@@ -7,24 +7,28 @@
 #ifndef __ASM_ARM_ARCH_DWMMC_H
 #define __ASM_ARM_ARCH_DWMMC_H
 
-#define DWMCI_CLKSEL           0x09C
-#define DWMCI_CLKSEL64         0x0a8
-#define DWMCI_SET_SAMPLE_CLK(x)        (x)
-#define DWMCI_SET_DRV_CLK(x)   ((x) << 16)
-#define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
+#include <linux/bitops.h>
 
-#define EMMCP_MPSBEGIN0                0x1200
-#define EMMCP_SEND0            0x1204
-#define EMMCP_CTRL0            0x120C
+#define DWMCI_CLKSEL                   0x09c
+#define DWMCI_CLKSEL64                 0x0a8
+#define DWMCI_SET_SAMPLE_CLK(x)                (x)
+#define DWMCI_SET_DRV_CLK(x)           ((x) << 16)
+#define DWMCI_SET_DIV_RATIO(x)         ((x) << 24)
 
-#define MPSCTRL_SECURE_READ_BIT                (0x1<<7)
-#define MPSCTRL_SECURE_WRITE_BIT       (0x1<<6)
-#define MPSCTRL_NON_SECURE_READ_BIT    (0x1<<5)
-#define MPSCTRL_NON_SECURE_WRITE_BIT   (0x1<<4)
-#define MPSCTRL_USE_FUSE_KEY           (0x1<<3)
-#define MPSCTRL_ECB_MODE               (0x1<<2)
-#define MPSCTRL_ENCRYPTION             (0x1<<1)
-#define MPSCTRL_VALID                  (0x1<<0)
+/* Protector Register */
+#define DWMCI_EMMCP_BASE               0x1000
+#define EMMCP_MPSBEGIN0                        (DWMCI_EMMCP_BASE + 0x0200)
+#define EMMCP_SEND0                    (DWMCI_EMMCP_BASE + 0x0204)
+#define EMMCP_CTRL0                    (DWMCI_EMMCP_BASE + 0x020c)
+
+#define MPSCTRL_SECURE_READ_BIT                BIT(7)
+#define MPSCTRL_SECURE_WRITE_BIT       BIT(6)
+#define MPSCTRL_NON_SECURE_READ_BIT    BIT(5)
+#define MPSCTRL_NON_SECURE_WRITE_BIT   BIT(4)
+#define MPSCTRL_USE_FUSE_KEY           BIT(3)
+#define MPSCTRL_ECB_MODE               BIT(2)
+#define MPSCTRL_ENCRYPTION             BIT(1)
+#define MPSCTRL_VALID                  BIT(0)
 
 /* CLKSEL Register */
 #define DWMCI_DIVRATIO_BIT             24

diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index a9e240fd91d6fe5cb7bf903ace2f28b33aca9e55..c8bf89d6d3552c1e0ebcaccc48a08087cbf3f596 100644 (file)
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -45,7 +45,7 @@ struct exynos_dwmmc_variant {
        u32 quirks;             /* quirk flags - see DWMCI_QUIRK_... */
 };
 
-/* Exynos implmentation specific drver private data */
+/* Exynos implementation specific driver private data */
 struct dwmci_exynos_priv_data {
 #ifdef CONFIG_DM_MMC
        struct dwmci_host host;
@@ -121,10 +121,7 @@ static int exynos_dwmmc_set_sclk(struct dwmci_host *host, unsigned long rate)
        return 0;
 }
 
-/*
- * Function used as callback function to initialise the
- * CLKSEL register for every mmc channel.
- */
+/* Configure CLKSEL register with chosen timing values */
 static int exynos_dwmci_clksel(struct dwmci_host *host)
 {
        struct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host);
@@ -163,7 +160,7 @@ static u8 exynos_dwmmc_get_ciu_div(struct dwmci_host *host)
                                & DWMCI_DIVRATIO_MASK) + 1;
 }
 
-unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq)
+static unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq)
 {
        unsigned long sclk;
        u8 clk_div;
@@ -204,7 +201,6 @@ static void exynos_dwmci_board_init(struct dwmci_host *host)
                             MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
        }
 
-       /* Set to timing value at initial time */
        if (priv->sdr_timing)
                exynos_dwmci_clksel(host);
 }
@@ -214,8 +210,8 @@ static int exynos_dwmmc_of_to_plat(struct udevice *dev)
 {
        struct dwmci_exynos_priv_data *priv = dev_get_priv(dev);
        struct dwmci_host *host = &priv->host;
-       int err = 0;
        u32 div, timing[2];
+       int err;
 
        priv->chip = (struct exynos_dwmmc_variant *)dev_get_driver_data(dev);
 
@@ -223,9 +219,8 @@ static int exynos_dwmmc_of_to_plat(struct udevice *dev)
        const void *blob = gd->fdt_blob;
        int node = dev_of_offset(dev);
 
-       /* Extract device id for each mmc channel */
+       /* Obtain device ID for current MMC channel */
        host->dev_id = pinmux_decode_periph_id(blob, node);
-
        host->dev_index = dev_read_u32_default(dev, "index", host->dev_id);
        if (host->dev_index == host->dev_id)
                host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;
@@ -241,10 +236,6 @@ static int exynos_dwmmc_of_to_plat(struct udevice *dev)
                host->dev_index = 2; /* SD card */
 #endif
 
-       /* Get the bus width from the device node (Default is 4bit buswidth) */
-       host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
-
-       /* Set the base address from the device node */
        host->ioaddr = dev_read_addr_ptr(dev);
        if (!host->ioaddr) {
                printf("DWMMC%d: Can't get base address\n", host->dev_index);
@@ -255,17 +246,17 @@ static int exynos_dwmmc_of_to_plat(struct udevice *dev)
                div = priv->chip->div;
        else
                div = dev_read_u32_default(dev, "samsung,dw-mshc-ciu-div", 0);
+
        err = dev_read_u32_array(dev, "samsung,dw-mshc-sdr-timing", timing, 2);
        if (err) {
                printf("DWMMC%d: Can't get sdr-timings\n", host->dev_index);
                return -EINVAL;
        }
-
        priv->sdr_timing = DWMCI_SET_SAMPLE_CLK(timing[0]) |
                           DWMCI_SET_DRV_CLK(timing[1]) |
                           DWMCI_SET_DIV_RATIO(div);
 
-       /* sdr_timing didn't assigned anything, use the default value */
+       /* sdr_timing wasn't set, use the default value */
        if (!priv->sdr_timing) {
                if (host->dev_index == 0)
                        priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL;
@@ -284,6 +275,7 @@ static int exynos_dwmmc_of_to_plat(struct udevice *dev)
                                   DWMCI_SET_DIV_RATIO(div);
        }
 
+       host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
        host->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0);
        host->bus_hz = dev_read_u32_default(dev, "clock-frequency", 0);
 
@@ -396,8 +388,8 @@ U_BOOT_DRIVER(exynos_dwmmc_drv) = {
        .of_match       = exynos_dwmmc_ids,
        .of_to_plat     = exynos_dwmmc_of_to_plat,
        .bind           = exynos_dwmmc_bind,
-       .ops            = &dm_dwmci_ops,
        .probe          = exynos_dwmmc_probe,
+       .ops            = &dm_dwmci_ops,
        .priv_auto      = sizeof(struct dwmci_exynos_priv_data),
        .plat_auto      = sizeof(struct exynos_mmc_plat),
 };