usb: onboard-hub: Add i2c initialization for usb5744 hub
Add i2c initialization hook and set usb5744 platform
data with function having required i2c initialization sequence.
Apart from the USB command attach, prevent the hub from suspend.
when the “USB Attach with SMBUS (0xAA56)” command is issued to the hub,
the hub is getting enumerated and then it puts in a suspend mode.
This causes the hub to NAK any SMBUS access made by the SMBUS Master
during this period and not able to see the hub's slave address while
running the "i2c probe" command.
Prevent the MCU from the putting the HUB in suspend mode through register
write. The BYPASS_UDC_SUSPEND bit (Bit 3) of the RuntimeFlags2 register at
address 0x411D controls this aspect of the hub. The BYPASS_UDC_SUSPEND
bit in register 0x411Dh must be set to ensure that the MCU is always
enabled and ready to respond to SMBus runtime commands. This register
needs to be written before the USB attach command is issued.
The byte sequence is as follows:
Slave addr: 0x2d 00 00 05 00 01 41 1D 08
Slave addr: 0x2d 99 37 00
Slave addr: 0x2d AA 56 00
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Reviewed-by: Marek Vasut <marex@denx.de>
usb: onboard-hub: add support for Microchip USB5744
Add support for the Microchip USB5744 USB3.0 and USB2.0 Hub.
The usb5744 driver trigger hub reset signal after soft reset.
The usb5744 hub need to reset after the phy initialization,
which toggles the gpio.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Reviewed-by: Marek Vasut <marex@denx.de>
As part of the reset, sets the direction of the pin to output before
toggling the pin. Delay of millisecond is added in between low and
high to meet the setup and hold time requirement of the reset.
Update the usb2514 hub_data with the reset delay and power on
delay values.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Reviewed-by: Marek Vasut <marex@denx.de>
Tom Rini [Sun, 24 Nov 2024 21:41:32 +0000 (15:41 -0600)]
Merge patch series "Fix device removal order for Apple dart iommu"
Janne Grunau <j@jannau.net> says:
Starting with v2024.10 dev_iommu_dma_unmap calls during device removal
trigger a NULL pointer dereference in the Apple dart iommu driver. The
iommu device is removed before its user. The sparsely used DM_FLAG_VITAL
flag is intended to describe this dependency. Add it to the driver.
Adding this flag is unfortunately not enough since the boot routines
except the arm one simply remove all drivers. Add and use a new function
which calls
dm_remove_devioce_flags(DM_REMOVE_ACTIVE_ALL | DM_REMOVE_NON_VITAL);
dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
to ensure this order dependency is head consistently.
Janne Grunau [Sat, 23 Nov 2024 21:44:05 +0000 (22:44 +0100)]
dm: Add dm_remove_devices_active() for ordered device removal
This replaces dm_remove_devices_flags() calls in all boot
implementations to ensure non vital devices are consistently removed
first. All boot implementation except arch/arm/lib/bootm.c currently
just call dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL). This can result
in crashes when dependencies between devices exists. The driver model's
design document describes DM_FLAG_VITAL as "indicates that the device is
'vital' to the operation of other devices". Device removal at boot
should follow this.
Instead of adding dm_remove_devices_flags() with (DM_REMOVE_ACTIVE_ALL |
DM_REMOVE_NON_VITAL) everywhere add dm_remove_devices_active() which
does this.
Fixes a NULL pointer deref in the apple dart IOMMU driver during EFI
boot. The xhci-pci (driver which depends on the IOMMU to work) removes
its mapping on removal. This explodes when the IOMMU device was removed
first.
dm_remove_devices_flags() is kept since it is used for testing of
device_remove() calls in dm.
Janne Grunau [Sat, 23 Nov 2024 21:44:04 +0000 (22:44 +0100)]
iommu: apple: Mark device with DM_FLAG_VITAL
Avoids NULL pointer dereferences in apple_dart_unmap when the iommu
device is removed before its user. U-boot's device model does not track
dependencies between devices.
Observed on a M1 Ultra Mac Studio with v2024.10.
Acked-by: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Janne Grunau <j@jannau.net>
Ilias Apalodimas [Sun, 24 Nov 2024 09:00:03 +0000 (11:00 +0200)]
lmb: Correctly unmap and free memory on errors
We never free and unmap the memory on errors and we never unmap it when
freeing it. The latter won't cause any problems even on sandbox, but for
consistency always use unmap_sysmem()
Fixes: commit 22f2c9ed9f53 ("efi: memory: use the lmb API's for allocating and freeing memory") Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
efi_loader: allow EFI_LOADER_BOUNCE_BUFFER on all architectures
Commit 775f7657ba58 ("Kconfig: clean up the efi configuration status")
by mistake revoked commit dcd1b63b7072 ("efi_loader: allow
EFI_LOADER_BOUNCE_BUFFER on all architectures").
Fixes: 775f7657ba58 ("Kconfig: clean up the efi configuration status") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Tested-by: Loic Devulder <ldevulder@suse.com>
Marek Vasut [Fri, 22 Nov 2024 01:58:12 +0000 (02:58 +0100)]
arm64: dts: imx8mn: Include 32kHz oscillator clock in SPL DTs
Since 50cdd3f74af3 ("clk: imx: clk-imx8mn Fix nand and spi clock parent"),
drivers/clk/imx/clk-imx8mn.c clk_get_by_name(dev, "osc_24m", &osc_24m_clk)
fails with error -22 EINVAL in SPL. This is because clk_get_by_name() in the
end calls fdtdec_parse_phandle_with_args(), which iterates over all phandles
in clock-controller@30380000 { clocks = <&osc_32k>, <&osc_24m>, ... } node
'clocks' property in an attempt to find the "osc_24m" clock, but fails to
resolve the &osc_32k phandle and returns with -EINVAL.
Include the osc_32k clock in SPL DTs as a low risk fix for v2025.01 release.
This way, fdtdec_parse_phandle_with_args() can resolve both the osc_32k and
following osc_24m phandle and successfully look up the osc_24m clock.
Fixes: 50cdd3f74af3 ("clk: imx: clk-imx8mn Fix nand and spi clock parent") Signed-off-by: Marek Vasut <marex@denx.de> Tested-by: Adam Ford <aford173@gmail.com> #imx8mn-beacon
Ilias Apalodimas [Thu, 14 Nov 2024 14:29:15 +0000 (16:29 +0200)]
net: lwip: provide entropy to MBed TLS in one go
We currently provide entropy to mbedTLS using 8b chunks.
Take into account the 'len' parameter passed by MBed TLS to the entropy
gathering function instead. Note that the current code works because len
is always 128 (defined at compile time), therefore mbedtls_hardware_poll()
is called repeatedly and the buffer is filled correctly. But passing 'len'
to dm_rng_read() is both better and simpler.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Jerome Forissier [Mon, 18 Nov 2024 14:31:25 +0000 (15:31 +0100)]
net: lwip: fix get_udev_ipv4_info()
The local variables ipstr, maskstr and gwstr in static function
get_udev_ipv4_info() cannot be pointers to read-only data, since
they may be written to in case the device index is > 0. Therefore
make them char arrays allocated on the stack.
Tom Rini [Tue, 19 Nov 2024 14:05:26 +0000 (08:05 -0600)]
Revert "test: Update time tests to use unit-test asserts"
While at the base level, this conversion looks equivalent, we now see
both of these tests failing (due to exceeding their allowed margin for
being too slow) in Azure with a very high frequency.
Jerome Forissier [Fri, 22 Nov 2024 12:35:29 +0000 (13:35 +0100)]
net: lwip: fix dhcp_loop()
The local variables ipstr, maskstr and gwstr in static function
dhcp_loop() cannot be pointers to read-only data, since they may be
written to in case the device index is > 0. Therefore make them char
arrays allocated on the stack.
- UFS support is enabled for SC7280 and SM8150 platforms.
- Qualcomm dt-bindings headers are all dropped in favour of
dts/upstream.
- The SMMU driver now correctly handles stream ID 0 and is disabled in
EL2.
- Initial support for capsule updates (using the new dynamic UUIDs) is
added for the RB3 Gen 2 board alongside a new SCSI backend for DFU.
- CONFIG_PINCONF is enabled in qcom_defconfig.
- The vqmmc supply is now enabled for sdcard support on boards that need
it.
- A quirk is added for reading GPIOs on the PM8550 PMIC
Caleb Connolly [Sat, 12 Oct 2024 13:57:20 +0000 (15:57 +0200)]
qcom_defconfig: enable capsule update support
Enable all the necessary options for capsule updates to work, as well as
a few additional EFI features.
Capsule updates themselves are only enabled for the RB3 Gen 2, since the
exact details on where to flash U-Boot (or how to handle multiple boot
methods) has not been finalised for other boards.
Caleb Connolly [Sat, 12 Oct 2024 13:57:19 +0000 (15:57 +0200)]
mach-snapdragon: implement capsule update support
Qualcomm boards flash U-Boot a variety of partitions, implement support
for determining which slot U-Boot is running from, finding the correct
partition for that slot and configuring the appropriate DFU string.
Initially, we only support the RB3 Gen 2 where U-Boot is flashed to the
UEFI partition, and ignore handling of slots. In the future we will
additionally support booting U-Boot from other partitions (e.g. boot)
and correct handling for A/B.
Caleb Connolly [Sat, 12 Oct 2024 13:57:18 +0000 (15:57 +0200)]
disk: expose partition type flags
GPT partition tables include two bytes worth of vendor defined
attributes, per partition. ChromeOS and Qualcomm both use these (with
different encoding!) to handle A/B slot switching with a retry counter.
Expose these via the disk_partition struct so that they can be parsed by
the relevant board code.
This will be used on Qualcomm boards to determine which slot we're
booting on so that we can flash capsule updates to the correct one.
Neil Armstrong [Wed, 16 Oct 2024 07:43:56 +0000 (09:43 +0200)]
phy: qcom: ufs: drop unused ufsphy_v2_regs_layout
The ufsphy_v2_regs_layout is not used, drop it and fix:
phy-qcom-qmp-ufs.c:87:27: warning: ‘ufsphy_v2_regs_layout’ defined but not used [-Wunused-const-variable=]
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Neil Armstrong [Wed, 16 Oct 2024 09:16:18 +0000 (11:16 +0200)]
gpio: qcom_pmic: add again the quirk to skip GPIO configuration on PM8550
The qcom_pmic code is broken for new PMICs and should be fixed,
without the QUIRK the code is broken and the GPIOs don't work
anymore on SM8550 and SM8650 platforms.
Partially revert the revert and only add the quirk on the PM8550
PMIC, making the buttons and MMC detect gpio work again.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Neil Armstrong [Wed, 16 Oct 2024 09:17:16 +0000 (11:17 +0200)]
mmc: msm_sdhci: enable vqmmc at probe if available
On earlier platforms, the vqmmc regulator was enabled by the
previous bootloader, but on the newest (SM8650) it's not
and we need vqmmc to be enabled in order to have the card
to respond.
Michal Simek [Fri, 15 Nov 2024 14:31:02 +0000 (15:31 +0100)]
xilinx: Introduce XILINX_MINI configuration
There is no common symbol which mini configurations are using and recent
get_mem_top() changes adding 1.3kB without having a way to remove it.
That's why introduce new symbol which can be used for removing features
which are not requested by these configurations.
Michal Simek [Tue, 12 Nov 2024 13:58:48 +0000 (14:58 +0100)]
arm64: zynqmp: Set default RTC device at start
For RTC to start to operate there is a need to call the driver. The simple
way to do it is to set default RTC instance which will call the probe and
do basic initialization.
arm64: versal: Enable soft reset support for xspi flashes
Activate the xSPI Software Reset support, which will be
utilized to transition from octal DTR mode to legacy
mode during shutdown and boot (if enabled).
arm64: versal: Enable defconfig for Micron octal flashes
The Micron MT35 series octal flashes can be activated
through the configuration option CONFIG_SPI_FLASH_MT35XU.
To ensure their detection, enable this option in the
default defconfig for octal flashes.
Moving the hw_reset function from the controller driver to
the NOR framework has caused the OSPI reset not to be triggered
in the Cadence driver's probe function. As a result, reading the
flash ID during SPI calibration is incorrect, and the
CQSPI_REG_RD_DATA_CAPTURE is set with an invalid value.This makes
it unable to read the flash ID properly.
To solve this problem, it's suggested to skip SPI calibration and
instead retrieve the read_delay directly from the device tree.
Skipping SPI calibration doesn't bring harm since there's no need
for the flash golden values stored during SPI calibration.
Instead, they are now read during the spi_nor_read_id call in the
NOR framework.
test: cmd/hash: check return value of ut_check_console_line
ut_check_console_line() does include an assert.
Pass the result to ut_assertok().
Addresses-Coverity-ID: 514958 Error handling issues Fixes: 7dfafcd65ef3 ("test: unit test for hash command") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Jerome Forissier [Tue, 12 Nov 2024 15:44:29 +0000 (16:44 +0100)]
Kconfig: describe NET, NO_NET, LWIP_DEBUG and LWIP_ASSERT
Some Kconfig symbols introduced in commit 8cb330355bd5 ("net: introduce
alternative implementation as net/lwip/") need a full description. The
NET symbol needs one, too.
Tom Rini [Mon, 18 Nov 2024 14:24:06 +0000 (08:24 -0600)]
Merge patch series "Fix boot failure due to misaligned DMA buffer"
Nam Cao <namcao@linutronix.de> says:
We observed the following sporadic boot failure while booting from MMC
device:
=> boot
CACHE: Misaligned operation at range [9efa25f8, 9efa27f8]
CACHE: Misaligned operation at range [9efa25f8, 9efa27f8]
CACHE: Misaligned operation at range [9efa25f8, 9efa27f8]
CACHE: Misaligned operation at range [9efa25f8, 9efa27f8]
** Booting bootflow 'mmc@2194000.bootdev.part_1' with extlinux
Ignoring unknown command: �D���D��
Boot failed (err=-14)
The reason is because while allocating buffer to read a file from MMC,
alignment of 1 byte is used. Thus, the buffer doesn't work for performing
DMA, and garbage data is read.
While looking at this issue, I also noticed that if no alignment specified
(align=0) then fs_read_alloc() is documented to use the default. But the
default is no alignment. Therefore, other users of fs_read_alloc() which
specify align=0 may be broken as well.
The first patch changes extlinux_read_bootflow() to use proper buffer
alignment for DMA.
The second patch changes the default alignment of fs_read_alloc() to be
DMA-suitable, to fix other potential bugs.
Nam Cao [Thu, 7 Nov 2024 15:01:06 +0000 (16:01 +0100)]
fs: Use ARCH_DMA_MINALIGN as default alignment for fs_read_alloc()
The comment above fs_read_alloc() explains:
@align: Alignment to use for memory allocation (0 for default)
However, in the actual implementation, there is no alignment when @align is
zero.
This current default is probably fine for most cases. But for some block
devices which transfer data via DMA, ARCH_DMA_MINALIGN is needed.
Change the default alignment to ARCH_DMA_MINALIGN.
Fixes: de7b5a8a1ac0 ("fs: Create functions to load and allocate a file") Signed-off-by: Nam Cao <namcao@linutronix.de> Tested-by: Javier Fernandez Pastrana <javier.pastrana@linutronix.de>
Nam Cao [Thu, 7 Nov 2024 15:01:05 +0000 (16:01 +0100)]
boot: extlinux: Fix unaligned buffer for reading data from file system
extlinux_read_bootflow() allocates a buffer to read from file system
without any alignment.
But for some block devices which transfer data via DMA, ARCH_DMA_MINALIGN
alignment is required. For example, due to misaligned buffer, the below
boot failure is observed.
=> boot
CACHE: Misaligned operation at range [9efa25f8, 9efa27f8]
CACHE: Misaligned operation at range [9efa25f8, 9efa27f8]
CACHE: Misaligned operation at range [9efa25f8, 9efa27f8]
CACHE: Misaligned operation at range [9efa25f8, 9efa27f8]
** Booting bootflow 'mmc@2194000.bootdev.part_1' with extlinux
Ignoring unknown command: �D���D��
Boot failed (err=-14)
Change the buffer alignment to ARCH_DMA_MINALIGN.
Fixes: 31aefaf89a5b ("bootstd: Add an implementation of distro boot") Signed-off-by: Nam Cao <namcao@linutronix.de> Tested-by: Javier Fernandez Pastrana <javier.pastrana@linutronix.de>
- Two changes from Heinrich:
- One is adding some missing TPM files for proper maintenance.
- The second addresses Coverity-ID: 356664 replacing a mempcy() which
has undefined behavior with memmove()
fs: btrfs: hide duplicate 'Cannot lookup file' error on 'load'
Running commands such as 'load mmc 2:1 $addr $path' when path does not
exists will print an error twice if the file does not exist, e.g.:
```
Cannot lookup file boot/boot.scr
Failed to load 'boot/boot.scr'
```
(where the first line is printed by btrfs and the second by common fs
code)
Historically other filesystems such as ext4 or fat have not been
printing a message here, so do the same here to avoid duplicate.
The other error messages in this function are also somewhat redundant,
but bring useful diagnostics if they happen somewhere, so have been left
as printf.
Note that if a user wants no message to be printed for optional file
loads, they have to check for file existence first with other commands
such as 'size'.
Fix the critical thermal threshold for i.MX processors, this was changed
while moving the code from imx8m/imx9 directories into a shared place.
There is no need to keep the critical threshold 5 degrees less than the
SoC maximum temperature threshold, what is actually going to happen in
practice is that we are going to power-off the board when the SoC is
still within its working temperature range.
In addition to that this is a change in the actual behavior, that is
introducing a regression to users, and it was hidden within a software
refactoring.
Fixes: d0fe80890ab1 ("imx: Generalize fixup_thermal_trips") Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
drivers: bootcount: Add ZynqMP specific bootcount support
Add native support of the bootcount mechanism in the ZynqMP by
utilising internal PMU registers. The Persistent Global Storage
Registers of the Platform Management Unit can keep their value
during reboot cycles unless there is a POR reset, making them
appropriate for the bootcount mechanism.
Peter Korsgaard [Tue, 5 Nov 2024 16:21:36 +0000 (17:21 +0100)]
boot/image-board.c: boot_get_fpga(): pass compatible flag to fpga_load()
For E.G. signed FPGA bitstreams, similar to how it is done for the FPGA
loading from SPL since commit 71f1a5392aad ("spl: fit: pass real compatible
flags to fpga_load()").
Michal Simek [Fri, 25 Oct 2024 11:56:07 +0000 (13:56 +0200)]
arm64: versal: Do not define do_reset() if sysreset is enabled
If sysreset is enabled reset_cpu is defined in sysreset uclass that's why
it can't be in platform/board code.
The same change was done by commit f1bc214b0024 ("arm64: zynqmp: Do not
define do_reset() if sysreset is enabled").
Padmarao Begari [Mon, 4 Nov 2024 12:27:50 +0000 (17:57 +0530)]
arm64: zynqmp: Fix r5 mode for cpu release command
The cpu release command for r5 mode (lockstep/split) argument
accepts only string. But the zynqmp tcminit command accepts
string or number for r5 mode (lockstep/split or 0/1) argument.
To fix the r5 mode argument, the common argument (lockstep/split
or 0/1) is used across different u-boot commands. Use the strcmp()
instead of strncmp() to make uniform the r5 mode (lockstep/split
or 0/1) for the zynqmp tcminit and cpu release command.
Sughosh Ganu [Fri, 25 Oct 2024 17:27:24 +0000 (22:57 +0530)]
xilinx: use get_mem_top() to compute ram_top
Use the get_mem_top function to compute the value of ram_top. This was
earlier done through LMB API's, which are no longer available till
after relocation. Use get_mem_top() instead to compute the ram_top
value.
Sughosh Ganu [Fri, 25 Oct 2024 17:27:23 +0000 (22:57 +0530)]
common: memtop: add logic to detect ram_top
Add generic logic to determine the ram_top value for boards. Earlier,
this was achieved in an indirect manner through a set of LMB API's.
That has since changed so that the LMB code is available only after
relocation. Replace those LMB calls with a single call to
get_mem_top() to determine the value of ram_top.
In the message string " %s[%d]\t[0x%llx-0x%llx], 0x%08llx bytes flags: "
a comma is missing before flags.
To avoid increasing the code size replace '0x%' by '%#'.
Printing the size with leading zeros but not the addresses does not really
make sense. Remove the leading zeros from the size output.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
[trini: Fix test/cmd/bdinfo.c for these changes] Signed-off-by: Tom Rini <trini@konsulko.com>
When calling decode_addr_size() we must pass the size of the device-tree
property and not sizeof(void *).
Fixes: 90469da3da0d ("upl: Add support for reading a upl handoff")
Addresses-Coverity-ID: 510459 Wrong sizeof argument Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Loic Poulain [Thu, 31 Oct 2024 09:15:31 +0000 (10:15 +0100)]
lib: rsa: Set conventional salt length RSA-PSS parameter
RFC 3447 says that Typical salt length are either 0 or the length
of the output of the digest algorithm, RFC 4055 also recommends
hash value length as the salt length. Moreover, By convention,
most of the signing infrastructures/libraries use the length of
the digest algorithm (such as google cloud kms:
https://cloud.google.com/kms/docs/algorithms).
If the salt-length parameter is not set, openssl default to the
maximum allowed value, which is a openssl 'specificity', so this
works well for local signing, but restricts compatibility with
other engines (e.g pkcs11/libkmsp11):
```
returning 0x71 from C_SignInit due to status INVALID_ARGUMENT:
at rsassa_pss.cc:53: expected salt length for key XX is 32,
but 478 was supplied in the parameters
Could not obtain signature: error:41000070:PKCS#11 module::Mechanism invalid
```
To improve compatibility, we set the default RSA-PSS salt-length
value to the conventional one. A further improvement could consist
in making it configurable as signature FIT node attribute.
Quentin Schulz [Mon, 11 Nov 2024 13:20:49 +0000 (14:20 +0100)]
Makefile: fix empty MK_ARCH when using ccache
One can use ccache by prefixing the typical CROSS_COMPILE value with
"ccache " (e.g. "ccache aarch64-gnu-linux-" for Aarch64). This however
makes the MK_ARCH empty because sed won't find a match anymore since it
expects the CROSS_COMPILE value to start with the actual toolchain (with
an unlimited number of white spaces before).
This is failing builds since commit 7506c1566998 ("sandbox: Report host
default-filename in native mode").
Add "ccache" prefix to ignore but participate in the matching regex used
by sed to identify the target architecture.
examples: make glue and demo code compatible with 64-bit
Commit f9886bc60f42 ("Added arm64 assembly for examples/api crt0")
added a 64-bit target for the examples but did not adjust the demo
code to be 64-bit compatible.
Change variable size for pointers.
Use %p to print pointers.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Commit f9886bc60f42 ("Added arm64 assembly for examples/api crt0") tried to
add arm64 support to the examples but crt0.S does not even build for
qemu_arm64_defconfig with CONFIG_API=y, CONFIG_EXAMPLES=y:
examples/api/crt0.S: Assembler messages:
examples/api/crt0.S:32: Error:
expected a register at operand 1 -- `ldr ip,=search_hint'
examples/api/crt0.S:33: Error:
unexpected register type at operand 1 -- `str sp,[ip]'
make[2]: *** [scripts/Makefile.build:292: examples/api/crt0.o] Error 1
Do not define _start twice.
Use valid register names.
Move syscall_ptr and search_hint to the data section to avoid an invalid
relocation.
Fixes: f9886bc60f42 ("Added arm64 assembly for examples/api crt0") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tom Rini [Thu, 14 Nov 2024 16:49:30 +0000 (10:49 -0600)]
Merge patch series "cmd: hash: correct parameter count check"
Heinrich Schuchardt <heinrich.schuchardt@canonical.com> says:
Since commit 348ea878508d ("cmd: hash: fix param count check") the hash
command cannot be used without the optional variable name parameter if
CONFIG_HASH_VERIFY=y. 'hash sha1 $loadaddr $filesize' returns
CMD_RET_USAGE.
The minimum number of arguments is four no matter if verification is
enabled or not.
Tom Rini [Thu, 14 Nov 2024 16:48:07 +0000 (10:48 -0600)]
Merge patch series "Apply SoM overlays on phyCORE-AM6xx SoMs"
Wadim Egorov <w.egorov@phytec.de> says:
Our SoMs are available in multiple configurations, managed via device
tree overlays. To determine the specific variant in use, we read the
EEPROM and apply the appropriate overlays during boot to the device tree
used by the OS.
Apply overlays for phyCORE-AM62x and phyCORE-AM64x SoMs.
Future K3 SoMs will be able to reuse this logic and overlays.
projects / u-boot.git / log