]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
clk: mediatek: mt7622: move INFRA_TRNG to the bottom
authorChristian Marangi <ansuelsmth@gmail.com>
Sat, 3 Aug 2024 08:43:21 +0000 (10:43 +0200)
committerTom Rini <trini@konsulko.com>
Mon, 19 Aug 2024 22:15:26 +0000 (16:15 -0600)
Move INFRA_TRNG clock to the bottom of the clk ID to match upstream
linux order. This is in preparation of OF_UPSTREAM.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
drivers/clk/mediatek/clk-mt7622.c
include/dt-bindings/clock/mt7622-clk.h

index 4a7c5faff1a6cc33268e5b2872949deb3e45f615..8f173b794533b13299b095ebcc08fab2dddbe590 100644 (file)
@@ -382,11 +382,11 @@ static const struct mtk_gate_regs infra_cg_regs = {
 
 static const struct mtk_gate infra_cgs[] = {
        GATE_INFRA(CLK_INFRA_DBGCLK_PD, CLK_TOP_AXI_SEL, 0),
-       GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 2),
        GATE_INFRA(CLK_INFRA_AUDIO_PD, CLK_TOP_AUD_INTBUS_SEL, 5),
        GATE_INFRA(CLK_INFRA_IRRX_PD, CLK_TOP_IRRX_SEL, 16),
        GATE_INFRA(CLK_INFRA_APXGPT_PD, CLK_TOP_F10M_REF_SEL, 18),
        GATE_INFRA(CLK_INFRA_PMIC_PD, CLK_TOP_PMICSPI_SEL, 22),
+       GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 2),
 };
 
 /* pericfg */
index 78804f40307558b9dacc37a93fe03b09ff548d81..2f36abcf8aeb190d9bbdb7fd4536f9890f821154 100644 (file)
 /* INFRACFG */
 
 #define CLK_INFRA_DBGCLK_PD            0
-#define CLK_INFRA_TRNG                 1
-#define CLK_INFRA_AUDIO_PD             2
-#define CLK_INFRA_IRRX_PD              3
-#define CLK_INFRA_APXGPT_PD            4
-#define CLK_INFRA_PMIC_PD              5
+#define CLK_INFRA_AUDIO_PD             1
+#define CLK_INFRA_IRRX_PD              2
+#define CLK_INFRA_APXGPT_PD            3
+#define CLK_INFRA_PMIC_PD              4
+#define CLK_INFRA_TRNG                 5
 
 /* PERICFG */