ddr: marvell: a38x: fix write leveling suplementary algo

commit ce62bef8fac559e27245259882e45f19cdc293ad upstream.

- fix JIRA A7K8K-5056
- remove TEST_PATTERN write at the load patern stage earlier to WL SUP stage
- the WL SUP stage already writes this pattern to the memory, if the pattern exist at the memory
  then the algorithm will fail, since it think that there are no phase to correct

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>

diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
index 979f3530b791d240a608827cc337fadb6ef24b98..5fd9a052fa0da45b81991f77fedb426cdcc02c09 100644 (file)
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
@@ -864,8 +864,11 @@ int ddr3_tip_load_all_pattern_to_mem(u32 dev_num)
                              DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3)));
        }
 
-       for (pattern = 0; pattern < PATTERN_LAST; pattern++)
+       for (pattern = 0; pattern < PATTERN_LAST; pattern++) {
+               if (pattern == PATTERN_TEST)
+                       continue;
                ddr3_tip_load_pattern_to_mem(dev_num, pattern);
+       }
 
        return MV_OK;
 }