From: Vignesh Raghavendra <vigneshr@ti.com>
Date: Mon, 22 Apr 2019 16:13:33 +0000 (+0530)
Subject: board: ti: am654: select SYS_DISABLE_DCACHE_OPS for arm64 build
X-Git-Tag: v2025.01-rc5-pxa1908~3000^2~24
X-Git-Url: http://git.dujemihanovic.xyz/img/%22http:/www.sics.se/static/gitweb.css?a=commitdiff_plain;h=c14f3c31112653f5c5a34b748e9defbd3bc5a8ef;p=u-boot.git

board: ti: am654: select SYS_DISABLE_DCACHE_OPS for arm64 build

AM654 SoC is IO coherent wrt A53 cores, therefore enable
SYS_DISABLE_DCACHE_OPS to avoid cache operations in A53
SPL/U-Boot.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---

diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig
index d4b36dbb42..98172c28f5 100644
--- a/board/ti/am65x/Kconfig
+++ b/board/ti/am65x/Kconfig
@@ -11,6 +11,7 @@ config TARGET_AM654_A53_EVM
 	bool "TI K3 based AM654 EVM running on A53"
 	select ARM64
 	select SOC_K3_AM6
+	select SYS_DISABLE_DCACHE_OPS
 
 config TARGET_AM654_R5_EVM
 	bool "TI K3 based AM654 EVM running on R5"