From f9539a9caa12195870cfc3b0cf6150755aeb2e52 Mon Sep 17 00:00:00 2001
From: Shaohui Xie <Shaohui.Xie@freescale.com>
Date: Mon, 25 Mar 2013 07:40:18 +0000
Subject: [PATCH] powerpc/p2041: fix serdes reference clock frequency display
for PC board
PC board has different serdes clock setting with PB board, it uses same
serdes frequency setting on bank2 as on bank1. PC board can be distingushed
from PB board by checking CPLD version, if running on PC board, then fix
the serdes reference clock frequency of bank2.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
---
board/freescale/p2041rdb/p2041rdb.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index a706a6d00c..44d3e0c618 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -227,6 +227,17 @@ int misc_init_r(void)
"'00' is unsupported\n");
else
actual[i] = freq[i][clock];
+
+ /*
+ * PC board uses a different CPLD with PB board, this CPLD
+ * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB
+ * board has cpld_ver_sub = 0, and pcba_ver = 4.
+ */
+ if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) &&
+ (CPLD_READ(pcba_ver) == 5)) {
+ /* PC board bank2 frequency */
+ actual[i] = freq[i-1][clock];
+ }
}
for (i = 0; i < NUM_SRDS_BANKS; i++) {
--
2.39.5