From ca7fb12cc18e80d14cca9570aec1d544f5d8c169 Mon Sep 17 00:00:00 2001 From: Nikhil Badola <nikhil.badola@freescale.com> Date: Fri, 26 Jun 2015 16:59:21 +0530 Subject: [PATCH] armv8/lsch3/config: Define CONFIG_SYS_CACHELINE_SIZE for LS2085A Define CONFIG_SYS_CACHELINE_SIZE for LS2085A which is required by USB XHCI stack for alignment Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> --- arch/arm/include/asm/arch-fsl-lsch3/config.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 8675e91fca..032cfd80eb 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -10,6 +10,7 @@ #include <fsl_ddrc_version.h> #define CONFIG_SYS_PAGE_SIZE 0x10000 +#define CONFIG_SYS_CACHELINE_SIZE 64 #ifndef L1_CACHE_BYTES #define L1_CACHE_SHIFT 6 -- 2.39.5