From 891180923ef9ac67b822718948310a4b5c33cd5b Mon Sep 17 00:00:00 2001 From: Udit Kumar <u-kumar1@ti.com> Date: Thu, 21 Sep 2023 22:30:38 +0530 Subject: [PATCH] clk: ti: clk-k3: Notify AVS driver upon setting clock rate AVS is enabled at R5 SPL stage, on few platforms like J721E and J7200 clk-k3 is used instead if clk-sci driver. Add support in clk-k3 driver as well to notify AVS driver on setting clock rate so that voltage is changed accordingly. Cc: Keerthy <j-keerthy@ti.com> Signed-off-by: Udit Kumar <u-kumar1@ti.com> --- drivers/clk/ti/clk-k3.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c index ba925fa3c4..10f7240f77 100644 --- a/drivers/clk/ti/clk-k3.c +++ b/drivers/clk/ti/clk-k3.c @@ -11,6 +11,7 @@ #include <errno.h> #include <soc.h> #include <clk-uclass.h> +#include <k3-avs.h> #include "k3-clk.h" #define PLL_MIN_FREQ 800000000 @@ -242,7 +243,11 @@ static ulong ti_clk_set_rate(struct clk *clk, ulong rate) const struct clk_ops *ops; ulong new_rate, rem; ulong diff, new_diff; + int freq_scale_up = rate >= ti_clk_get_rate(clk) ? 1 : 0; + if (IS_ENABLED(CONFIG_K3_AVS0) && freq_scale_up) + k3_avs_notify_freq(data->map[clk->id].dev_id, + data->map[clk->id].clk_id, rate); /* * We must propagate rate change to parent if current clock type * does not allow setting it. @@ -339,6 +344,10 @@ static ulong ti_clk_set_rate(struct clk *clk, ulong rate) } } + if (IS_ENABLED(CONFIG_K3_AVS0) && !freq_scale_up) + k3_avs_notify_freq(data->map[clk->id].dev_id, + data->map[clk->id].clk_id, rate); + return new_rate; } -- 2.39.5