From 541b2adf080bf9299161fe9af29659633e03d7db Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 15 Mar 2021 17:25:51 +1300
Subject: [PATCH] x86: coral: Drop TPM and ACPI interrupts from TPL
These devices are not actually built in TPL but are currently active in
the TPL devicetree. For of-platdata-inst this means that we will try to
generate devices for them, which fails.
Update them to be active only in U-Boot proper.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/x86/dts/chromebook_coral.dts | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts
index 2ffe3b423c..d109a38759 100644
--- a/arch/x86/dts/chromebook_coral.dts
+++ b/arch/x86/dts/chromebook_coral.dts
@@ -100,7 +100,7 @@
clk: clock {
compatible = "intel,apl-clk";
#clock-cells = <1>;
- u-boot,dm-pre-reloc;
+ u-boot,dm-pre-proper;
};
cpus {
@@ -141,7 +141,7 @@
};
acpi_gpe: general-purpose-events {
- u-boot,dm-pre-reloc;
+ u-boot,dm-pre-proper;
reg = <IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>;
compatible = "intel,acpi-gpe";
interrupt-controller;
@@ -423,7 +423,7 @@
compatible = "intel,apl-i2c", "snps,designware-i2c-pci";
reg = <0x0200b210 0 0 0 0>;
early-regs = <IOMAP_I2C2_BASE 0x1000>;
- u-boot,dm-pre-reloc;
+ u-boot,dm-pre-proper;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
@@ -434,7 +434,7 @@
tpm: tpm@50 {
reg = <0x50>;
compatible = "google,cr50";
- u-boot,dm-pre-reloc;
+ u-boot,dm-pre-proper;
u-boot,i2c-offset-len = <0>;
ready-gpios = <&gpio_n 28 GPIO_ACTIVE_LOW>;
interrupts-extended = <&acpi_gpe GPIO_28_IRQ
@@ -1233,5 +1233,5 @@
&rtc {
#address-cells = <1>;
#size-cells = <0>;
- u-boot,dm-pre-reloc;
+ u-boot,dm-pre-proper;
};
--
2.39.5