From 507e2d79c91441a0bb2cd3d0c31c8bfe3f8cec07 Mon Sep 17 00:00:00 2001 From: Joe D'Abbraccio <ljd015@freescale.com> Date: Mon, 24 Mar 2008 13:00:59 -0400 Subject: [PATCH] Modified the DDR SDRAM clock control register to delay MCK/MCK_B 3/4 clock With the original value of 1/2 clock cycle delay, the system ran relatively stable except when we run benchmarks that are intensive users of memory. When I run samba connected disk with a HDBENCH test, the system locks-up or reboots sporadically. Signed-off by: Joe D'Abbraccio <Joe.D'abbraccio@freescale.com> --- include/configs/MPC8349ITX.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 0e50186765..6b8b74dd96 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -156,7 +156,7 @@ #define CFG_MEMTEST_END 0x2000 #define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #ifdef CONFIG_HARD_I2C #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ -- 2.39.5