From 13022d852d5c233894fabb62279a2ae9e0355638 Mon Sep 17 00:00:00 2001 From: Chin Liang See <clsee@altera.com> Date: Wed, 21 Sep 2016 10:26:03 +0800 Subject: [PATCH] arm: socfpga: de0-nano-soc: Adding handoff for SDRAM ctrlcfg.extratime1 Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> --- board/terasic/de0-nano-soc/qts/sdram_config.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/terasic/de0-nano-soc/qts/sdram_config.h b/board/terasic/de0-nano-soc/qts/sdram_config.h index 7084797750..d96b28af82 100644 --- a/board/terasic/de0-nano-soc/qts/sdram_config.h +++ b/board/terasic/de0-nano-soc/qts/sdram_config.h @@ -42,6 +42,9 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 #define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -- 2.39.5