From: Saeed Nowshadi Date: Thu, 25 Jan 2024 08:07:58 +0000 (+0100) Subject: arm64: zynqmp: Add 'silabs, skip-recall' to all si570 clk nodes X-Git-Url: http://git.dujemihanovic.xyz/html/static/gitweb.css?a=commitdiff_plain;h=cbd87dae91b41db4685b18a53739bd8cd54e79f5;p=u-boot.git arm64: zynqmp: Add 'silabs, skip-recall' to all si570 clk nodes Without 'silabs,skip-recall' property, the driver on System Controller re-calibrates the output clock frequency at probe() time based on the NVRAM setting. This re-calibration causes a glitch on the output clock. At power-on, Versal is also booting and expecting a glitch-free clock for its correct operation. System Controller should skip the re-calibration step to prevent any clock instability for Versal. Signed-off-by: Saeed Nowshadi Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/bbb2322c94503f0e6b369c60312b7546500fad95.1706170068.git.michal.simek@amd.com --- diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index f1b0a4aa65..0b97fa3f28 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -449,6 +449,7 @@ factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_zsfp_clk"; + silabs,skip-recall; }; }; i2c@6 { /* USER_SI570_1 */ @@ -463,6 +464,7 @@ factory-fout = <100000000>; clock-frequency = <100000000>; clock-output-names = "si570_user1"; + silabs,skip-recall; }; }; @@ -560,6 +562,7 @@ factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk2"; + silabs,skip-recall; }; }; i2c@5 { /* LPDDR4_SI570_CLK1 */ @@ -574,6 +577,7 @@ factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk1"; + silabs,skip-recall; }; }; i2c@6 { /* HSDP_SI570 */ @@ -588,6 +592,7 @@ factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; + silabs,skip-recall; }; }; i2c@7 { /* 8A34001 - U219B and J310 connector */