From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Date: Wed, 4 Sep 2019 06:25:44 +0000 (+0000)
Subject: armv8: ls1028a: Updated serdes configuration for 0x13BB
X-Git-Tag: v2025.01-rc5-pxa1908~2784^2~1
X-Git-Url: http://git.dujemihanovic.xyz/html/static/gitweb.css?a=commitdiff_plain;h=116f75c7b310bb5087195416e309d5a292e04560;p=u-boot.git

armv8: ls1028a: Updated serdes configuration for 0x13BB

In SerDes protocol 0x13BB, lane C was erroneously assigned
to PCIE1, this is now updated to PCIE2

Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes
		     protocal support")

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
---

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c
index 5835a3a69e..313f3f1e8a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c
@@ -24,7 +24,7 @@ static struct serdes_config serdes1_cfg_tbl[] = {
 	{0xDDDD, {PCIE1, PCIE1, PCIE1, PCIE1} },
 	{0xE031, {SXGMII1, QXGMII2, NONE, SATA1} },
 	{0xB991, {SXGMII1, SGMII1, SGMII2, PCIE1} },
-	{0xBB31, {SXGMII1, QXGMII2, PCIE1, PCIE1} },
+	{0xBB31, {SXGMII1, QXGMII2, PCIE2, PCIE1} },
 	{0xCC31, {SXGMII1, QXGMII2, PCIE2, PCIE2} },
 	{0xBB51, {SXGMII1, QSGMII_B, PCIE2, PCIE1} },
 	{0xBB38, {SGMII_T1, QXGMII2, PCIE2, PCIE1} },