]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
arm64: zynqmp: Configure SoC RTC on SOM
authorMichal Simek <michal.simek@amd.com>
Wed, 23 Oct 2024 06:09:23 +0000 (08:09 +0200)
committerMichal Simek <michal.simek@amd.com>
Tue, 12 Nov 2024 08:01:46 +0000 (09:01 +0100)
Use RTC available in HW on Kria SOM without using emulation that's why
configure it properly and disable emulated one.
Power on reset value of RTC Calibration register without battery backup is
not matching with crystal frequency which leads to RTC time drift. That's
why write CALIB_WRITE register with crystal frequency (0x7FFF). There is
also an option to write zero so that Linux will set default value (0x7FFF)
in driver probe but calibration 0 is not permited by DT schema.

Co-developed-by: Srinivas Goud <srinivas.goud@amd.com>
Signed-off-by: Srinivas Goud <srinivas.goud@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9b684faeec85381b9b8fe796aaebc2ee79f17b8e.1729663761.git.michal.simek@amd.com
arch/arm/dts/zynqmp-sm-k26-revA.dts
configs/xilinx_zynqmp_kria_defconfig

index 8056f6b176edbd3f1f7506ac8e69206e9bc6c63e..8c43ade9405361a357f126ceb5d26f7635ddee19 100644 (file)
 
 &rtc {
        status = "okay";
+       calibration = <0x7fff>;
 };
 
 &lpd_dma_chan1 {
index dd4df0b2da175366f1a5e2e922b2534536942ee0..0dddf69c5d0591c5973fc39e1e1b0fcaa8503757 100644 (file)
@@ -187,7 +187,6 @@ CONFIG_DM_PWM=y
 CONFIG_PWM_CADENCE_TTC=y
 CONFIG_RESET_ZYNQMP=y
 CONFIG_DM_RTC=y
-CONFIG_RTC_EMULATION=y
 CONFIG_RTC_ZYNQMP=y
 CONFIG_SCSI=y
 CONFIG_ARM_DCC=y