ngpios = <208>;
};
+ sgpiom0: sgpiom@1e780500 {
+ compatible = "aspeed,ast2600-sgpiom";
+ reg = <0x1e780500 0x100>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scu ASPEED_CLK_APB2>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ bus-frequency = <1000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sgpm1_default>;
+ status = "disabled";
+ };
+
+ sgpiom1: sgpiom@1e780600 {
+ compatible = "aspeed,ast2600-sgpiom";
+ reg = <0x1e780600 0x100>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scu ASPEED_CLK_APB2>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ bus-frequency = <12000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sgpm2_default>;
+ status = "disabled";
+ };
+
gpio1: gpio@1e780800 {
compatible = "aspeed,ast2600-gpio";
reg = <0x1e780800 0x800>;
function = "PCIE1RC";
groups = "PCIE1RC";
};
+
+ pinctrl_sgpm1_default: sgpm1_default {
+ function = "SGPM1";
+ groups = "SGPM1";
+ };
+
+ pinctrl_sgpm2_default: sgpm2_default {
+ function = "SGPM2";
+ groups = "SGPM2";
+ };
};
{0x41c, BIT(31), 0},
};
+static struct aspeed_sig_desc sgpm1[] = {
+ {0x414, GENMASK(27, 24), 0},
+};
+
+static struct aspeed_sig_desc sgpm2[] = {
+ {0x6d0, GENMASK(7, 4), 0},
+};
+
static const struct aspeed_group_config ast2600_groups[] = {
{ "MAC1LINK", ARRAY_SIZE(mac1_link), mac1_link },
{ "MAC2LINK", ARRAY_SIZE(mac2_link), mac2_link },
{ "PWM14G1", ARRAY_SIZE(pwm14g1), pwm14g1 },
{ "PWM15G0", ARRAY_SIZE(pwm15g0), pwm15g0 },
{ "PWM15G1", ARRAY_SIZE(pwm15g1), pwm15g1 },
+ { "SGPM1", ARRAY_SIZE(sgpm1), sgpm1 },
+ { "SGPM2", ARRAY_SIZE(sgpm2), sgpm2 },
};
static int ast2600_pinctrl_get_groups_count(struct udevice *dev)