From cc1dd33f273f8c96cbd7539b4a2d1d7aa12773cd Mon Sep 17 00:00:00 2001
From: John Schmoller <jschmoller@xes-inc.com>
Date: Thu, 10 Mar 2011 16:09:26 -0600
Subject: [PATCH] mpc8[5/6]xx: Ensure POST word does not get reset
The POST word is stored in a spare register in the PIC on MPC8[5/6]xx
processors. When interrupt_init() is called, this register gets reset
which resulted in all POST_RAM POSTs not being ran due to the corrupted
POST word. To resolve this, store off POST word before the PIC is
reset, and restore it after the PIC has been initialized.
Signed-off-by: John Schmoller <jschmoller@xes-inc.com>
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
arch/powerpc/cpu/mpc85xx/interrupts.c | 16 ++++++++++++++++
arch/powerpc/cpu/mpc86xx/interrupts.c | 16 ++++++++++++++++
2 files changed, 32 insertions(+)
diff --git a/arch/powerpc/cpu/mpc85xx/interrupts.c b/arch/powerpc/cpu/mpc85xx/interrupts.c
index a62b031774..7ab71137f6 100644
--- a/arch/powerpc/cpu/mpc85xx/interrupts.c
+++ b/arch/powerpc/cpu/mpc85xx/interrupts.c
@@ -32,11 +32,23 @@
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
+#ifdef CONFIG_POST
+#include <post.h>
+#endif
int interrupt_init_cpu(unsigned int *decrementer_count)
{
ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
+#ifdef CONFIG_POST
+ /*
+ * The POST word is stored in the PIC's TFRR register which gets
+ * cleared when the PIC is reset. Save it off so we can restore it
+ * later.
+ */
+ ulong post_word = post_word_load();
+#endif
+
out_be32(&pic->gcr, MPC85xx_PICGCR_RST);
while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST)
;
@@ -78,6 +90,10 @@ int interrupt_init_cpu(unsigned int *decrementer_count)
pic->ctpr=0; /* 40080 clear current task priority register */
#endif
+#ifdef CONFIG_POST
+ post_word_store(post_word);
+#endif
+
return (0);
}
diff --git a/arch/powerpc/cpu/mpc86xx/interrupts.c b/arch/powerpc/cpu/mpc86xx/interrupts.c
index d8ad6d30d6..14821f4243 100644
--- a/arch/powerpc/cpu/mpc86xx/interrupts.c
+++ b/arch/powerpc/cpu/mpc86xx/interrupts.c
@@ -35,12 +35,24 @@
#include <mpc86xx.h>
#include <command.h>
#include <asm/processor.h>
+#ifdef CONFIG_POST
+#include <post.h>
+#endif
int interrupt_init_cpu(unsigned long *decrementer_count)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_pic_t *pic = &immr->im_pic;
+#ifdef CONFIG_POST
+ /*
+ * The POST word is stored in the PIC's TFRR register which gets
+ * cleared when the PIC is reset. Save it off so we can restore it
+ * later.
+ */
+ ulong post_word = post_word_load();
+#endif
+
pic->gcr = MPC86xx_PICGCR_RST;
while (pic->gcr & MPC86xx_PICGCR_RST)
;
@@ -74,6 +86,10 @@ int interrupt_init_cpu(unsigned long *decrementer_count)
pic->ctpr = 0; /* 40080 clear current task priority register */
#endif
+#ifdef CONFIG_POST
+ post_word_store(post_word);
+#endif
+
return 0;
}
--
2.39.5