From cb4820725e9fc409c5cbc8e83054a6ed522d2111 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@pollux.denx.de>
Date: Thu, 18 Jan 2007 11:28:51 +0100
Subject: [PATCH] [PATCH] Fix: Compilerwarnings for SC3 board. The
EBC Configuration Register is now by CFG_EBC_CFG definable Added
JFFS2 support for the SC3 board.
Signed-off-by: Heiko Schocher <hs@denx.de>
---
board/sc3/sc3.c | 2 ++
cpu/ppc4xx/405gp_pci.c | 4 +---
cpu/ppc4xx/cpu_init.c | 5 ++---
drivers/cfi_flash.c | 6 +++---
include/configs/sc3.h | 39 ++++++++++++++++++++++++++-------------
5 files changed, 34 insertions(+), 22 deletions(-)
diff --git a/board/sc3/sc3.c b/board/sc3/sc3.c
index d94896ecd0..363a77d8a4 100644
--- a/board/sc3/sc3.c
+++ b/board/sc3/sc3.c
@@ -354,6 +354,8 @@ int board_early_init_f (void)
initUsbHost (&cpldConfig_1);
writeb (cpldConfig_1, CPLD_CONTROL_1);
#endif
+ /* FIXME: for what must we do this */
+ *(unsigned long *)0x79000080 = 0x0001;
return(0);
}
diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c
index 38a1305d7f..7134355635 100644
--- a/cpu/ppc4xx/405gp_pci.c
+++ b/cpu/ppc4xx/405gp_pci.c
@@ -380,7 +380,7 @@ void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
}
-#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) || defined (CONFIG_SOLIDCARD3)
+#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SOLIDCARD3))
/*
*As is these functs get called out of flash Not a horrible
@@ -406,7 +406,6 @@ static struct pci_controller hose = {
config_table: pci_405gp_config_table,
};
-#ifndef CONFIG_SOLIDCARD3
void pci_init_board(void)
{
/*we want the ptrs to RAM not flash (ie don't use init list)*/
@@ -414,7 +413,6 @@ void pci_init_board(void)
hose.config_table = pci_405gp_config_table;
pci_405gp_init(&hose);
}
-#endif
#endif
diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index e2aa867c94..ae24591087 100644
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -313,9 +313,8 @@ cpu_init_f (void)
mtebc(pb7cr, CFG_EBC_PB7CR);
#endif
-#if defined (CONFIG_SOLIDCARD3)
- mtebc(epcr, 0xb84ef000);
- *(unsigned long *)0x79000080 = 0x0001;
+#if defined (CFG_EBC_CFG)
+ mtebc(epcr, CFG_EBC_CFG);
#endif
#if defined(CONFIG_WATCHDOG)
diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c
index 8dc44997b8..665d8e7649 100644
--- a/drivers/cfi_flash.c
+++ b/drivers/cfi_flash.c
@@ -860,7 +860,7 @@ static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
*/
static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
{
-#if defined(__LITTLE_ENDIAN)
+#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SOLIDCARD3)
unsigned short w;
unsigned int l;
unsigned long long ll;
@@ -880,7 +880,7 @@ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
#endif
break;
case FLASH_CFI_32BIT:
-#if defined(__LITTLE_ENDIAN)
+#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SOLIDCARD3)
l = c;
l <<= 24;
cword->l = (cword->l >> 8) | l;
@@ -889,7 +889,7 @@ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
#endif
break;
case FLASH_CFI_64BIT:
-#if defined(__LITTLE_ENDIAN)
+#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SOLIDCARD3)
ll = c;
ll <<= 56;
cword->ll = (cword->ll >> 8) | ll;
diff --git a/include/configs/sc3.h b/include/configs/sc3.h
index 2d0278290a..a4a1605460 100644
--- a/include/configs/sc3.h
+++ b/include/configs/sc3.h
@@ -108,7 +108,8 @@
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "nand_args=setenv bootargs root=/dev/mtdblock4 rw\0" \
+ "nand_args=setenv bootargs root=/dev/mtdblock5 rw" \
+ "rootfstype=jffs2\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
@@ -164,18 +165,19 @@
#define CONFIG_COMMANDS \
(CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_NET | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_NAND | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_CACHE | \
- CFG_CMD_ELF )
+ CFG_CMD_PCI | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_NET | \
+ CFG_CMD_MII | \
+ CFG_CMD_PING | \
+ CFG_CMD_NAND | \
+ CFG_CMD_JFFS2 | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IDE | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_CACHE | \
+ CFG_CMD_ELF )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
@@ -404,6 +406,15 @@ extern unsigned long offsetOfEnvironment;
#define NAND_MAX_CHIPS 1
#define CFG_NAND_BASE 0x77D00000
+
+#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
+
+/* No command line, one static partition Partition 3 contains jffs2 rootfs */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nand0"
+#define CONFIG_JFFS2_PART_SIZE 0x00400000
+#define CONFIG_JFFS2_PART_OFFSET 0x00c00000
+
/*-----------------------------------------------------------------------
* Cache Configuration
*
@@ -516,6 +527,8 @@ extern unsigned long offsetOfEnvironment;
#undef CFG_EBC_PB7AP
#undef CFG_EBC_PB7CR
+#define CFG_EBC_CFG 0xb84ef000
+
#define CONFIG_SDRAM_BANK0 /* use the standard SDRAM initialization */
#undef CONFIG_SPD_EEPROM
--
2.39.5