From b34bc22bd9921547246c117fb95eb58bedaceff5 Mon Sep 17 00:00:00 2001
From: Ovidiu Panait <ovpanait@gmail.com>
Date: Wed, 12 Oct 2022 08:36:56 +0300
Subject: [PATCH] timer: xilinx-timer: use timer_conv_64() to fix timer wrap
around
Current xilinx_timer_get_count() implementation does not take into account
the periodic 32-bit wrap arounds, as it directly returns the 32-bit counter
register value. The roll-overs cause problems in the upper timer layers, as
generic timer code expects an incrementing 64-bit value from get_count() to
work correctly.
Add the missing 64-bit up-conversion to fix random hangs/delays in
__udelay().
Fixes: a36d86720f ("microblaze: Convert axi timer to DM driver")
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20221012053656.1492457-3-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
drivers/timer/xilinx-timer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/timer/xilinx-timer.c b/drivers/timer/xilinx-timer.c
index 75b4473b63..172fd9f929 100644
--- a/drivers/timer/xilinx-timer.c
+++ b/drivers/timer/xilinx-timer.c
@@ -40,7 +40,7 @@ static u64 xilinx_timer_get_count(struct udevice *dev)
regmap_read(priv->regs, TIMER_COUNTER_OFFSET, &value);
- return value;
+ return timer_conv_64(value);
}
static int xilinx_timer_probe(struct udevice *dev)
--
2.39.5