From 86be510f7b5443e7e937f696bfbe037fdc740b15 Mon Sep 17 00:00:00 2001
From: Ed Swarthout <Ed.Swarthout@freescale.com>
Date: Thu, 9 Oct 2008 00:29:27 -0500
Subject: [PATCH] mpc8572 additional end-point mode
mpc8572 supports all pcie controllers as end-points with cfg_host_agent=0.
Include host_agent == 0 decode for end-point determination.
This is not needed for the ds reference board since pcie3 will be a host
in order to connect to the uli chip. Include it here as a reference for
other mpc8572 boards.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
---
board/freescale/mpc8572ds/mpc8572ds.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index 66a0874ef1..74f1df2723 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -245,7 +245,7 @@ void pci_init_board(void)
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie2_hose;
int pcie_ep = (host_agent == 2) || (host_agent == 4) ||
- (host_agent == 6);
+ (host_agent == 6) || (host_agent == 0);
int pcie_configured = io_sel & 4;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
@@ -301,7 +301,7 @@ void pci_init_board(void)
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
- int pcie_ep = (host_agent == 1) || (host_agent == 4) ||
+ int pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
(host_agent == 5);
int pcie_configured = io_sel & 6;
--
2.39.5